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    Semiconductor device having supply voltage deboosting circuit
    1.
    发明授权
    Semiconductor device having supply voltage deboosting circuit 失效
    具有电源电压去抖动电路的半导体器件

    公开(公告)号：US5627493A

    公开(公告)日：1997-05-06

    申请号：US519249

    申请日：1995-08-25

    申请人： Yoshiaki Takeuchi ,  Hiroaki Tanaka ,  Masaru Koyanagi

    发明人： Yoshiaki Takeuchi ,  Hiroaki Tanaka ,  Masaru Koyanagi

    IPC分类号： G05F1/56 ,  G05F1/46 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413 ,  H03K19/00 ,  G05F3/02

    CPC分类号： G05F1/465 ,  G11C5/147

    摘要： The semiconductor device comprises: an internal supply voltage deboosting circuit for inputting an external supply voltage, deboosting the inputted external supply voltage, and outputting a deboosted voltage as an internal supply voltage; a first control circuit for deactivating the internal supply voltage deboosting circuit when the external supply voltage is lower than a predetermined value; and a second control circuit for outputting the external supply voltage as the internal supply voltage when the external supply voltage is lower than the predetermined value. When the external supply voltage is lower than a predetermined value, since the internal supply voltage deboosting circuit is deactivated by the first control circuit, the current consumption can be reduced. Further, since the external supply voltage is outputted as the internal supply voltage by the second control circuit, the deboosting operation is not required. The device is usable for different external supply voltages in spite of the same circuit configuration, while preventing the operational margin from being deteriorated.

    摘要翻译： 半导体器件包括：用于输入外部电源电压的内部电源电压去抖动电路，去除所输入的外部电源电压，并输出去激发的电压作为内部电源电压; 第一控制电路，用于当所述外部电源电压低于预定值时停止所述内部电源电压去抖动电路; 以及第二控制电路，用于当外部电源电压低于预定值时输出外部电源电压作为内部电源电压。 当外部电源电压低于预定值时，由于内部电源电压去保护电路被第一控制电路停用，所以可以减少电流消耗。 此外，由于通过第二控制电路输出外部电源电压作为内部电源电压，因此不需要去抖动操作。 尽管有相同的电路配置，该器件可用于不同的外部电源电压，同时防止操作裕度恶化。

    Sense amplifier having reduced coupling noise
    2.
    发明授权
    Sense amplifier having reduced coupling noise 失效
    具有减少耦合噪声的感应放大器

    公开(公告)号：US5168462A

    公开(公告)日：1992-12-01

    申请号：US585703

    申请日：1990-09-20

    申请人： Yoshiaki Takeuchi ,  Masaru Koyanagi

    发明人： Yoshiaki Takeuchi ,  Masaru Koyanagi

    IPC分类号： G11C11/401 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/06

    摘要： In a semiconductor memory device having plural pairs of bit lines and plural sense amplifiers, a gate electrode of a sense amplifier transistor for sensing potential of a first side of a first bit line pair is formed with an extension portion extending under and along the first side of a second bit line pair. A capacitance C.sub.B formed between the extension of the gate electrode and the first side of the second bit line pair is determined to be equal or larger than capacitance C.sub.A formed between the first side of the first bit line pair and the gate electrode. Since the potential of the first side of the bit line pair fluctuates roughly in phase with that of the second side of the same bit line pair, a harmful influence due to interference noise can be reduced, without increasing the chip layout area, by only modifying the shapes of the gate electrodes of the sense amplifier transistors.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5640355A

    公开(公告)日：1997-06-17

    申请号：US471507

    申请日：1995-06-06

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的相应参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5848011A

    公开(公告)日：1998-12-08

    申请号：US824737

    申请日：1997-03-26

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的各个参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Dynamic random access memory
    8.
    发明授权
    Dynamic random access memory 失效
    动态随机存取存储器

    公开(公告)号：US5282167A

    公开(公告)日：1994-01-25

    申请号：US813674

    申请日：1991-12-26

    申请人： Hiroaki Tanaka ,  Masaru Koyanagi

    发明人： Hiroaki Tanaka ,  Masaru Koyanagi

    IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  G11C7/02

    CPC分类号： G11C29/50 ,  G11C11/4085 ,  G11C11/401

    摘要： A DRAM according to the invention has noise-eliminating circuits. Each of the circuits has an output side thereof connected to a corresponding word line. At the time of a voltage stress examination, each of the circuits is controlled to be in an on-state thereby transmitting a voltage stress, input an input side thereof, to the word line. At the time of normal operation, the input side of the circuit is connected to an earth node, and each of the circuits is turned on and off in accordance with a signal output from a corresponding one of word line-selecting circuits or with the level of a corresponding one of the word lines.

    摘要翻译： 根据本发明的DRAM具有消噪电路。 每个电路的输出侧连接到相应的字线。 在电压胁迫检查时，每个电路被控制为导通状态，从而将电压应力传输到字线。 在正常操作时，电路的输入端连接到接地节点，并且每个电路根据从相应的一个字线选择电路输出的信号或者与电平 对应的一行字线。

    Level shift circuit
    9.
    发明授权
    Level shift circuit 有权
    电平移位电路

    公开(公告)号：US08736346B2

    公开(公告)日：2014-05-27

    申请号：US13524391

    申请日：2012-06-15

    申请人： Yuui Shimizu ,  Masaru Koyanagi

    发明人： Yuui Shimizu ,  Masaru Koyanagi

    IPC分类号： H03L5/00

    摘要： According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

    摘要翻译： 根据一个实施例，电平移位电路包括彼此连接的多个电平移位单元，其中输出电压的上升沿的延迟时间与输出电压的下降沿的延迟时间不同 。 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元的输出电压的下降沿的延迟时间补偿，并且输出电压的下降沿的延迟时间 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元补偿。

    Output buffer circuit, input buffer circuit, and input/output buffer circuit
    10.
    发明授权
    Output buffer circuit, input buffer circuit, and input/output buffer circuit 有权
    输出缓冲电路，输入缓冲电路，输入/输出缓冲电路

    公开(公告)号：US08405432B2

    公开(公告)日：2013-03-26

    申请号：US12963114

    申请日：2010-12-08

    申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

    发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

    IPC分类号： H03K3/01

    CPC分类号： H03K19/00384 ,  H03K19/01721

    摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

    摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。