公开(公告)号：US06809953B2

公开(公告)日：2004-10-26

申请号：US10440277

申请日：2003-05-16

申请人： Kenji Toyoda ,  Michihito Ueda ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Toru Iwata ,  Jun Kajiwara

发明人： Kenji Toyoda ,  Michihito Ueda ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Toru Iwata ,  Jun Kajiwara

IPC分类号： G11C1122

CPC分类号： H02M3/07 ,  H02M3/073

摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.

摘要翻译： 电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。 输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

公开(公告)号：US07053693B2

公开(公告)日：2006-05-30

申请号：US10765175

申请日：2004-01-28

申请人： Kenji Toyoda ,  Michihito Ueda ,  Kiyoshi Morimoto ,  Kiyoyuki Morita

发明人： Kenji Toyoda ,  Michihito Ueda ,  Kiyoshi Morimoto ,  Kiyoyuki Morita

IPC分类号： G05F1/10

CPC分类号： G11C11/4087 ,  G11C11/22 ,  G11C11/4074

摘要： A voltage generating circuit comprising a capacitor (4), a ferroelectric capacitor (6) serially connected to the capacitor (4), an output terminal (11), a capacitor (10) which grounds the output terminal (11), a supply voltage supplying terminal (13), a switch (1) which connects the supply voltage supplying terminal (13) and the connecting node (N1) of the two capacitors (4, 6), and a switch (9) which connects the connecting node (N1) and output terminal (11); wherein during a first period, with the two switches (1) and (9) placed in the OFF state, a terminal (3) is grounded and a terminal (7) is provided with a supply voltage; wherein during a second period, the terminal (3) is provided with the supply voltage and the switch (9) is placed in the ON state; wherein during a third period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is grounded; wherein during a fourth period, the terminal (7) is provided with the supply voltage; and wherein thereafter the first through fourth periods are repeated.

摘要翻译： 一种电压产生电路，包括电容器（4），串联连接到电容器（4）的铁电电容器（6），输出端子（11），接地输出端子（11）的电容器（10） 供给端子（13），连接电源电压端子（13）和两个电容器（4,6）的连接节点（N1）的开关（1）和连接节点 （N 1）和输出端子（11）; 其中在第一时段期间，当两个开关（1）和（9）处于断开状态时，端子（3）接地，端子（7）被提供有电源电压; 其中在第二时段期间，端子（3）设置有电源电压，开关（9）置于ON状态; 其中，在第三时段期间，开关（9）处于断开状态，开关（1）置于导通状态，端子（7）接地; 其中在第四时段期间，所述端子（7）被提供有电源电压; 此后重复第一至第四周期。

公开(公告)号：US06949780B2

公开(公告)日：2005-09-27

申请号：US10847323

申请日：2004-05-18

申请人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

发明人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

IPC分类号： H01L27/10 ,  G11C27/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： G11C27/005 ,  G11C11/54 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

公开(公告)号：US06844582B2

公开(公告)日：2005-01-18

申请号：US10434358

申请日：2003-05-09

申请人： Michihito Ueda ,  Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoyuki Morita

发明人： Michihito Ueda ,  Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoyuki Morita

IPC分类号： G06N3/063 ,  G11C27/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L45/00 ,  H01L29/76 ,  H01L27/108 ,  G06F15/18 ,  G06G7/00

CPC分类号： H01L27/11502 ,  G06N3/0635 ,  G11C11/54 ,  G11C27/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11507 ,  H01L27/11521 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/1203 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/144

摘要： A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.

摘要翻译： 本发明的半导体器件的学习方法包括具有倍增器作为突触的神经器件，其中重量根据输入重量电压而变化，并且用作处理模拟数据的神经网络系统，其包括步骤A的步骤A 向神经装置输入预定的输入数据并计算神经装置的输出的目标值相对于输入数据与实际输出之间的误差;步骤B，通过改变神经元的重量来计算误差的变化量; 之后的乘法器，以及基于误差变化量来改变乘法器的权重的步骤C，其中在步骤B和C中，在输入用于将权重设定为基本恒定值的复位电压之后， 重量电压，通过输入与要变化的重量相对应的重量电压来改变重量。

公开(公告)号：US06847071B2

公开(公告)日：2005-01-25

申请号：US10161696

申请日：2002-06-05

申请人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

发明人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

IPC分类号： H01L27/10 ,  G11C27/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： G11C27/005 ,  G11C11/54 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

摘要翻译： 在电位产生装置中，N型MIS晶体管的源极相互连接到P型MIS晶体管的源极，并且还连接到输出端子。 N型MIS晶体管54的漏极连接到用于提供电源电压VDD的电源电压供应部分，并且P型MIS晶体管的漏极连接到地。 此外，N型MIS晶体管的衬底电位为接地电压VSS，P型MIS晶体管56的衬底电位为电源电压VDD。 因此，它构成为用于从源极输出的源极跟随器电路。 通过利用该电位产生装置可以获得用于在NOR操作和NAND操作之间稳定切换的逻辑变换电路。

公开(公告)号：US06847543B2

公开(公告)日：2005-01-25

申请号：US10684419

申请日：2003-10-15

申请人： Kenji Toyoda ,  Kiyoyuki Morita

发明人： Kenji Toyoda ,  Kiyoyuki Morita

IPC分类号： G11C14/00 ,  G11C16/02 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C14/00 ,  G11C14/0063 ,  G11C14/0072 ,  G11C14/0081 ,  G11C14/009

摘要： A non-volatile memory circuit comprising first and second transistors (101, 102) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a first inverter is formed; third and fourth transistors (103, 104) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a second inverter is formed; a fifth transistor (105) provided with a gate, which is connected to a word line (107), and which is connected between a first bit line (108) and an input terminal of the second inverter; a sixth transistor (106) provided with a gate, which is connected to the word line (107), and which is connected between a second bit line (109) and an input terminal of the first inverter; and first and second resistor elements (114, 115) which are serially connected to the first and second inverters, respectively, wherein the input terminal and an output terminal of the first inverter are connected to an output terminal and the input terminal of the second inverter, respectively, and the resistance values of the first and second resistor elements (114, 115), which are connected to a ground line (111), are electrically variable.

摘要翻译： 一种非易失性存储器电路，包括每个具有栅极和漏极的第一和第二晶体管（101,102），其中这些晶体管的栅极彼此连接，并且这些晶体管的漏极彼此连接，由此第一 逆变器形成; 每个具有栅极和漏极的第三和第四晶体管（103,104），其中这些晶体管的栅极彼此连接，并且这些晶体管的漏极彼此连接，从而形成第二反相器; 具有连接到字线（107）并连接在第一位线（108）和第二反相器的输入端子之间的栅极的第五晶体管（105） 设置有与所述字线（107）连接的栅极的第六晶体管（106），连接在第二位线（109）和第一反相器的输入端子之间; 以及分别与第一和第二反相器串联连接的第一和第二电阻器元件（114,115），其中第一反相器的输入端子和输出端子连接到输出端子，第二反相器的输入端子 并且连接到接地线（111）的第一和第二电阻器元件（114,115）的电阻值是电可变的。

公开(公告)号：US06845032B2

公开(公告)日：2005-01-18

申请号：US10785031

申请日：2004-02-25

申请人： Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoshi Morimoto

发明人： Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoshi Morimoto

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H03K3/356 ,  H03K17/693 ,  H03K19/0948 ,  H03K19/185

CPC分类号： G11C11/22 ,  H03K17/693

摘要： Non-volatile latch circuit 10 of the present invention comprises ferroelectric capacitor 1 provided with a first electrode 1a, second electrode 1b, and ferroelectric film 1c that lies between these electrodes; reset terminal Tre that is connected to first electrode 1a and a CMOS inverter element 2 that is connected to second electrode 1b of ferroelectric capacitor 1; voltage switching terminal Tpl that applies a voltage to second electrode 1b; switching element 5 that is connected between second electrode 1b and second input terminal Tpl and switches a voltage applied to second electrode 1b; and set terminal Tse that applies a voltage for switching on or off switching element 5, wherein the voltage generated in second electrode 1b caused by polarization retained by ferroelectric film 1c is higher than the threshold voltage Vtn of NMISFET 4 of CMOS inverter element 2.

摘要翻译： 本发明的非易失性锁存电路10包括设置有位于这些电极之间的第一电极1a，第二电极1b和铁电体膜1c的铁电电容器1; 连接到第一电极1a的复位端子Tre和连接到铁电电容器1的第二电极1b的CMOS反相器元件2; 向第二电极1b施加电压的电压切换端子Tpl; 开关元件5，其连接在第二电极1b和第二输入端子Tpl之间，并切换施加到第二电极1b的电压; 并设置施加用于接通或关断开关元件5的电压的端子Tse，其中由铁电体膜1c保持的极化所引起的第二电极1b中产生的电压高于CMOS反相器元件2的NMISFET 4的阈值电压Vtn。

公开(公告)号：US20060020893A1

公开(公告)日：2006-01-26

申请号：US11234108

申请日：2005-09-26

申请人： Kenji Toyoda ,  Hideo Hibino

发明人： Kenji Toyoda ,  Hideo Hibino

IPC分类号： G11B27/00

CPC分类号： G11B27/00 ,  G11B19/022 ,  G11B27/105 ,  G11B27/11 ,  G11B27/326 ,  G11B27/329 ,  G11B2220/20 ,  G11B2220/65 ,  H04N5/781

摘要： An image playback apparatus and in image recording apparatus are designed to permit image playback from a selected position in an image file recorded to a directly accessible memory, such as a magnetic disk. During recording of an image file, the user can designate one or more candidate playback start positions in the file, and corresponding pointers are stored as part of the image file. When the file is to be played back, the playback apparatus accesses the pointer(s) and allows the user to select playback from the corresponding position(s) in the image file. Also the playback apparatus can rewrite pointers in an image file, whereby the user can designate candidate starting positions for future playback of the file.

公开(公告)号：US06737977B2

公开(公告)日：2004-05-18

申请号：US10040629

申请日：2002-01-09

申请人： Takayuki Nishikawa ,  Shoichi Oka ,  Koji Sakamoto ,  Takeshi Wada ,  Yasuyuki Kawano ,  Kenji Toyoda ,  Naoya Nagasawa ,  Shinji Kirihata

发明人： Takayuki Nishikawa ,  Shoichi Oka ,  Koji Sakamoto ,  Takeshi Wada ,  Yasuyuki Kawano ,  Kenji Toyoda ,  Naoya Nagasawa ,  Shinji Kirihata

IPC分类号： G08B1710

CPC分类号： G08B17/06 ,  G08B17/107 ,  G08B17/113 ,  G08B29/183

摘要： An improved fire detector unit has a plastic base defining a smoke chamber for detection of a smoke density in terms of light scattering due to the smoke particles in the smoke chamber. The base carries a circuit board mounting a light emitting element, a light receiving element, and other components forming a fire detecting circuit responsible for generating a fire warning signal based upon the detected smoke density. A metal-made electromagnetic shield is molded into the base to protect the light receiving element from electromagnetic radiation noises. The electromagnetic shield includes a ground terminal for connection with a ground line of the circuit board. In addition, terminal pins are molded into the base for electrical and physical connection of the circuit board to the base.

摘要翻译： 改进的火灾探测器单元具有限定烟室的塑料基座，用于根据烟雾室中的烟雾颗粒在光散射方面检测烟雾浓度。 底座承载安装发光元件的电路板，光接收元件和形成火灾检测电路的其他部件，该电路负责基于检测到的烟雾浓度产生火警警告信号。 金属制的电磁屏蔽件被模制到基座中以保护光接收元件免受电磁辐射噪声。 电磁屏蔽包括用于与电路板的接地线连接的接地端子。 此外，端子销被模制到基座中，用于将电路板与基座的电气和物理连接。

公开(公告)号：US4341448A

公开(公告)日：1982-07-27

申请号：US125274

申请日：1980-02-27

申请人： Kenji Toyoda ,  Haruo Hirano

发明人： Kenji Toyoda ,  Haruo Hirano

IPC分类号： G01J1/02 ,  G03B7/00

CPC分类号： G03B7/09976

摘要： In a light receiving element assembly in a camera, a light receiving element chip is provided in a first package and an IC chip for treating the output signal of the light receiving element is provided in a second package. A portion of the second package is extended so that a conductor pattern extended from the IC is provided on the extension. The output terminal of the light receiving element housed in the first package is connected to said pattern by soldering.

摘要翻译： 在相机中的光接收元件组件中，光接收元件芯片设置在第一封装中，并且用于处理光接收元件的输出信号的IC芯片设置在第二封装中。 第二包装的一部分被延伸，使得从扩展件上提供从IC延伸的导体图案。 容纳在第一封装中的光接收元件的输出端子通过焊接连接到所述图案。