公开(公告)号：US20230307361A1

公开(公告)日：2023-09-28

申请号：US17901644

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11551

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/11578 ,  H01L27/11551

Abstract: A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

公开(公告)号：US20230395498A1

公开(公告)日：2023-12-07

申请号：US18178008

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Tomoyuki TAKEISHI

IPC: H01L23/528 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27 ,  H10B43/40 ,  G11C16/04

CPC classification number: H01L23/5283 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27 ,  H10B43/40 ,  G11C16/0483

Abstract: A semiconductor storage device includes a first layer including a first surface and a second surface located opposite to the first surface. The first layer includes a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells. A second layer includes a third surface and a fourth surface located opposite to the third surface. The second layer includes a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells. The first layer and the second layer are joined together on the first surface and the third surface.

公开(公告)号：US20230411344A1

公开(公告)日：2023-12-21

申请号：US18175902

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Tomoyuki TAKEISHI

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/98 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2224/8084 ,  H01L2224/80905 ,  H01L2224/98 ,  H01L2924/1434

Abstract: In a method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate to a first principal surface, on which the first structure is formed, of the first substrate. The supporting substrate is higher in rigidity than the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The third substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the third substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

公开(公告)号：US20230307396A1

公开(公告)日：2023-09-28

申请号：US17901448

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/06 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.


PX1>PY1   (1)



PY2>PX2   (2)

公开(公告)号：US20230197672A1

公开(公告)日：2023-06-22

申请号：US17930988

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Ai MORI ,  Hiroaki ASHIDATE

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/74 ,  H01L2224/74 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a magnification difference acquirer configured to acquire a value of difference in magnification between a first substrate and a second substrate. The apparatus further includes a deformation amount determiner configured to determine a value of deformation amount of a chuck that holds the first or second substrate, based on the value of the difference in magnification. The apparatus further includes a gap determiner configured to determine a value of a gap between the first substrate and the second substrate, based on the value of the deformation amount. The apparatus further includes a bonding controller configured to control the deformation amount to the determined value and control the gap to the determined value, before the first substrate and the second substrate are bonded together.

公开(公告)号：US20230411322A1

公开(公告)日：2023-12-21

申请号：US18176189

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Tomoyuki TAKEISHI

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/603 ,  H01L21/302 ,  H01L21/02 ,  H01L29/68

CPC classification number: H01L24/06 ,  H01L21/76865 ,  H01L21/603 ,  H01L21/302 ,  H01L21/02521 ,  H01L21/02123 ,  H01L29/685

Abstract: A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

公开(公告)号：US20250029956A1

公开(公告)日：2025-01-23

申请号：US18777303

申请日：2024-07-18

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Hisashi KATO ,  Hiroaki ASHIDATE ,  Masayoshi TAGAMI

IPC: H01L25/065 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.

公开(公告)号：US20240324195A1

公开(公告)日：2024-09-26

申请号：US18612553

申请日：2024-03-21

Applicant: Kioxia Corporation

Inventor： Hakuba KITAGAWA ,  Mariko SUMIYA ,  Kohei NAKAMURA ,  Hiroaki ASHIDATE ,  Jun TAKAGI ,  Masayuki FUKUMOTO

IPC: H10B41/35 ,  H10B41/10 ,  H10B41/20

CPC classification number: H10B41/35 ,  H10B41/10 ,  H10B41/20

Abstract: A semiconductor device manufacturing method of embodiments includes: forming an insulating film on an outer peripheral portion of a surface of a first substrate; after forming the insulating film, forming a silicon layer in contact with the surface inside the insulating film; and forming a porous silicon layer by making the silicon layer inside the insulating film porous using an anodization method.

公开(公告)号：US20230397425A1

公开(公告)日：2023-12-07

申请号：US18182765

申请日：2023-03-13

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Tomoyuki TAKEISHI

IPC: H10B43/35 ,  H01L23/528 ,  H10B43/27 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L23/5283 ,  H10B43/27 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cell array layers. Each of the plurality of the memory cell array layers includes a plurality of memory cells. Each of the plurality of the memory cells includes a multi-layered body. The multi-layered body has a staircase structure including an inclined portion. The multi-layered body has a plurality of electrode layers having a plurality of end portions. The positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure. Two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween. The inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface.

公开(公告)号：US20230395499A1

公开(公告)日：2023-12-07

申请号：US18180442

申请日：2023-03-08

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Hisashi KATO ,  Tomoyuki TAKEISHI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/20 ,  H10B43/20

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/20 ,  H10B43/20

Abstract: In one embodiment, a semiconductor device includes a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, disposed on the first pad, and being in contact with the first pad. The device further includes a third pad provided in the second insulator, and disposed above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, disposed on the third pad, and being in contact with the third pad. Furthermore, a shape of the third or fourth pad is different from a shape of the first or second pad.