公开(公告)号：US20230309310A1

公开(公告)日：2023-09-28

申请号：US17930889

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Yuta SAITO ,  Shinji MORI ,  Hiroyuki YAMASHITA ,  Satoshi NAGASHIMA ,  Kazuhiro MATSUO ,  Kota TAKAHASHI ,  Shota KASHIYAMA ,  Keiichi SAWA ,  Junichi KANEYAMA

IPC: H01L27/1158 ,  G11C5/06 ,  H01L27/1157

CPC classification number: H01L27/1157 ,  G11C5/063 ,  H01L27/1158

Abstract: A semiconductor device of embodiments includes: a semiconductor layer containing silicon (Si); a first insulating layer provided in a first direction of the semiconductor layer; a second insulating layer surrounded by the semiconductor layer in a first cross section perpendicular to the first direction and containing silicon (Si) and oxygen (O); a third insulating layer surrounded by the second insulating layer in the first cross section and containing a metal element and oxygen (O); and a conductive layer surrounded by the first insulating layer in a second cross section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced from the semiconductor layer.

公开(公告)号：US20240121962A1

公开(公告)日：2024-04-11

申请号：US18461326

申请日：2023-09-05

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA ,  Shota KASHIYAMA ,  Tadashi IGUCHI ,  Takuya NISHIKAWA

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor device includes a stacked film with first insulating films and electrode layers alternately stacked in a first direction. The device further includes a columnar portion extending in the first direction and provided in a first region of the stacked film. The columnar portion forms memory cells at its intersections with the electrode layers. The device further includes a support column portion provided in a second region and extending in the first direction. A conductive plug is provided on a first electrode layer among the electrode layers in the second region. A first side surface of the support column portion faces a second side surface of the plug and the second side surface is concave in a direction toward the first side surface.

公开(公告)号：US20230023327A1

公开(公告)日：2023-01-26

申请号：US17807050

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA ,  Yefei HAN

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78

Abstract: A semiconductor storage device according to an embodiment includes a substrate, a first word line, a second word line, a first channel, a first memory film, a second channel, a second memory film, a first insulating layer, a first source line, and a first drain line. The second word line is separated from the first word line in a second direction. The first channel is aligned with the first word line in a third direction. The second channel is aligned with the second word line in the third direction. The first insulating layer is positioned between the first word line and the second word line in the second direction and between the first channel and the second channel in the second direction. The first source line and first drain line extend in the second direction.

公开(公告)号：US20210091112A1

公开(公告)日：2021-03-25

申请号：US17010451

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Yumi NAKAJIMA ,  Satoshi NAGASHIMA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/544

Abstract: According to one embodiment, a semiconductor device comprising: a first stacked structure in which first insulating layers and first conductive layers are alternately stacked; a second stacked structure in which second insulating layers and second conductive layers are alternately stacked; a first memory pillar provided in the first stacked structure; a first dividing structure dividing the first conductive layers; a second memory pillar provided within the second stacked structure and connected to the first memory pillar; a second dividing structure dividing the second conductive layers; a first alignment mark pillar provided in the first stacked structure and projecting from the first stacked structure; a second alignment mark pillar provided on the first alignment mark pillar; an alignment mark surrounded by the second alignment mark pillar.

公开(公告)号：US20220085060A1

公开(公告)日：2022-03-17

申请号：US17191217

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Ryota NARASAKI ,  Weili CAI ,  Satoshi NAGASHIMA ,  Takayuki ISHIKAWA ,  Yusuke SHIMADA ,  Yefei HAN

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A semiconductor storage device includes a first conductive layer; a first insulating layer between the first and second conductive layers; a second insulating layer between the first conductive layer and the first insulating layer; a third insulating layer between the second conductive layer and the first insulating layer; a fourth insulating layer between the second conductive layer and the third conductive layer; a fifth insulating layer between the second conductive layer and the fourth insulating layer; and a sixth insulating layer between the third conductive layer and the fourth insulating layer. The first conductive layer has a first surface. The second conductive layer has a second surface. A barrier conductive film containing at least one of nitrogen (N) or titanium (Ti) is provided on the first surface and the second surface.

公开(公告)号：US20240276721A1

公开(公告)日：2024-08-15

申请号：US18439898

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Kohei DATE ,  Kenji AOYAMA ,  Keisuke SUDA ,  Minami TANAKA ,  Satoshi NAGASHIMA

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductor layers including a first conductor layer as an uppermost layer; a plurality of memory pillars penetrating the conductor layers; and a member that includes a first portion extending in the conductor layers and a plurality of second portions RT provided apart from each other on the uppermost layer side of the conductor layers, and divides the conductor layers in a direction in a substrate surface; wherein a lower surface of the second portion is located below an upper surface of the first conductor layer, and an upper surface of the second portion is wider in a width in the direction, than the lower surface of the second portion and than the first portion.

公开(公告)号：US20240096418A1

公开(公告)日：2024-03-21

申请号：US18460203

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device includes a first stacked body, a second stacked body, an interposed portion, and a columnar body. The interposed portion is disposed between the first stacked body and the second stacked body. The columnar body includes a first columnar portion extending in a first direction inside the first stacked body, a second columnar portion extending in the first direction inside the second stacked body, and a connection portion disposed in the interposed portion and connecting the first columnar portion to the second columnar portion. At least part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.

公开(公告)号：US20240040785A1

公开(公告)日：2024-02-01

申请号：US18330661

申请日：2023-06-07

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A memory device includes first and second conductive layers aligned in a first direction; a memory pillar including first and second portions serving as first and second memory cells in a region where the second conductive layer overlaps the first conductive layer in the first direction; a first insulating member arranged between the first and second conductive layers in a region where the second conductive layer does not overlap the first conductive layer in the first direction; and a second insulating member intersecting with the first conductive layer in a region where the second insulating member overlaps the first insulating member in the first direction. An upper end of the second insulating member is separated from a lower end of the first insulating member.

公开(公告)号：US20230091827A1

公开(公告)日：2023-03-23

申请号：US17692711

申请日：2022-03-11

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA ,  Hidenori MIYAGAWA ,  Atsushi TAKAHASHI ,  Shota KASHIYAMA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes a substrate, a semiconductor layer extending in a first direction, a first conductive layer extending in a second direction and opposed to the semiconductor layer, an electric charge accumulating layer disposed between the semiconductor layer and the first conductive layer, and a first contact electrode extending in the first direction and connected to the first conductive layer. The first contact electrode has one end in the first direction farther from the substrate than the first conductive layer, the other end in the first direction closer to the substrate than the first conductive layer. The first conductive layer includes a first part opposed to the semiconductor layer and a second part connected to the first contact electrode. The second part has a thickness in the first direction larger than a thickness in the first direction of the first part.

公开(公告)号：US20220271054A1

公开(公告)日：2022-08-25

申请号：US17397376

申请日：2021-08-09

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor memory device includes a semiconductor substrate extending in a first and a second directions, memory blocks arranged in the first direction, and an inter-block structure disposed between the memory blocks. The memory block includes conductive layers, first semiconductor layers, and electric charge accumulating portions. The conductive layers are arranged in the third direction, and extend in the second direction. The first semiconductor layers extend in the third direction and are opposed to the conductive layers. The electric charge accumulating portions are disposed between the conductive layers and the first semiconductor layers. The inter-block structure includes a second semiconductor layer extending in the second direction and the third direction. The first semiconductor layers and second semiconductor layers are a part of the semiconductor substrate.