公开(公告)号：US20150016497A1

公开(公告)日：2015-01-15

申请号：US13955676

申请日：2013-07-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0029 ,  H04L7/02 ,  H04L7/033 ,  H04L2025/03598

Abstract: In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Abstract translation: 在所描述的实施例中，使用基于数字信号处理的SERDES装置来产生样本判定的方法包括：将模拟信号转换为数字信号，均衡数字信号，选择主CDR环路中的相位检测器的输入，计算相位差 信号，通过第一内插滤波器组产生对于最后均衡级的信号的相位偏移，产生控制信号以通过相位偏移适配环路来控制由第一内插滤波器组提供的相位，并且更新相位偏移值以产生 作出决定。 插入在均衡级之间的第一内插滤波器组被配置为产生到最后均衡级的相位偏移信号，并且响应于最后均衡级的相位偏移环被配置为调整由第一内插滤波器组提供的相位偏移 。

公开(公告)号：US20140241478A1

公开(公告)日：2014-08-28

申请号：US13776905

申请日：2013-02-26

Applicant: LSI CORPORATION

Inventor： Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L7/00

CPC classification number: H04L7/0004 ,  H04L7/007

Abstract: In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.

Abstract translation: 为了初始化在时钟和数据恢复（CDR）电路中使用的恢复时钟信号的相位，禁用正常的在线CDR处理。 模数转换器（ADC）采样的绝对值的总和是在ADC的模拟信号的每个单位间隔（UI）上为不同的时钟相位产生的，该模拟信号在指定的时间段内被采样。 选择对应于最大和的相位作为恢复的时钟信号的初始相位，用于启用的在线CDR处理，其中除了别的以外，还自动更新时钟相位，以确保ADC对模拟信号在中心附近进行采样 每个UI。

公开(公告)号：US08817867B1

公开(公告)日：2014-08-26

申请号：US13803435

申请日：2013-03-14

Applicant: LSI Corporation

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H03H7/30

CPC classification number: H04L27/01 ,  H04L25/03057 ,  H04L25/03885

Abstract: An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value.

Abstract translation: 一种包括均衡器电路，转换器电路和适配电路的装置。 均衡器电路可以被配置为响应于输入信号和梯度值而产生中间信号。 转换器电路可以被配置为响应于中间信号产生包括多个符号值的数字信号，包括主光标符号值。 适配电路可以被配置为响应于主光标符号值之前的多个符号值，主光标符号值之后的多个符号值和误差值来生成梯度值。

公开(公告)号：US20140204987A1

公开(公告)日：2014-07-24

申请号：US13745363

申请日：2013-01-18

Applicant: LSI CORPORATION

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil ,  Adam B. Healey

IPC: H04L1/20

CPC classification number: H04L1/20 ,  H04B17/345

Abstract: The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

Abstract translation: 本发明包括从建立在发射机和接收机之间的分散通信信道的输出接收信号，确定沿着在发射机和接收机之间建立的色散通信信道发送的信号的归一化奈奎斯特能量，并生成配置的映射表 以在基于归一化奈奎斯特能量的接收机接收的信号上识别在奈奎斯特频率处或接近奈奎斯特频率处的等于或高于所选公差电平的峰值。

公开(公告)号：US20150381393A1

公开(公告)日：2015-12-31

申请号：US14315759

申请日：2014-06-26

Applicant: LSI Corporation

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L25/03 ,  H04L7/033 ,  H04L25/02

CPC classification number: H04L25/03057 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0292 ,  H04L25/0307 ,  H04L25/03159 ,  H04L25/03885 ,  H04L2025/03636 ,  H04L2025/037

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。

公开(公告)号：US09083366B1

公开(公告)日：2015-07-14

申请号：US14220257

申请日：2014-03-20

Applicant: LSI Corporation

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H03M1/12 ,  H03M1/08 ,  H03M1/18

CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H04L7/002 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331

Abstract: A multi-channel analog-to-digital (ADC) converter coupled to a clock-and-data-recovery loop that has a plurality of clock-recovery circuits, each configured to set the sampling phase for a respective one of the ADC channels in a manner that causes the different sampling phases to be appropriately time-aligned with one another for time-interleaved operation of the ADC channels. In an example embodiment, an individual clock-recovery circuit comprises a phase detector and a loop filter. Loop filters corresponding to different clock-recovery circuits may be coupled to one another by having shared circuit elements in their frequency-tracking paths and/or by being configured to receive timing gradients from more than one phase detector, including the phase detector of a selected one of the clock-recovery circuits.

Abstract translation: 耦合到时钟和数据恢复环路的多通道模数（ADC）转换器，其具有多个时钟恢复电路，每个时钟恢复电路被配置为将ADC通道中的相应一个通道的采样相位设置在 使得不同采样相位彼此适当地时间对准以便ADC通道的时间交替操作的方式。 在示例实施例中，单独的时钟恢复电路包括相位检测器和环路滤波器。 对应于不同时钟恢复电路的环路滤波器可以通过在其频率跟踪路径中具有共享电路元件和/或通过被配置为从多于一个的相位检测器接收定时梯度来彼此耦合，包括所选择的相位检测器 其中一个时钟恢复电路。

公开(公告)号：US20150103961A1

公开(公告)日：2015-04-16

申请号：US14053069

申请日：2013-10-14

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Pervez M. Aziz

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04B1/10 ,  H04B1/30 ,  H04L7/0016 ,  H04L7/0278 ,  H04L25/03038

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.

Abstract translation: 一种在数据接收机等中使用的频带估计器，用于增强接收机中的时钟和数据恢复装置（CDR）的正弦抖动容限。 检测器使用两个不同抽头长度的移动平均滤波器，其接收来自CDR内的增益控制信号。 来自移动平均滤波器的输出信号被处理以通过测量在每个输出信号的转换之间发生的数字时钟周期来确定每个输出信号的半波时间周期。 将最长半波周期的时钟周期数与表示各种频带的频率限制的多个值进行比较，以确定哪个频带将抖动分类为增益控制信号。 确定的频带用于从查找表中选择一组用于CDR中的增益值。

公开(公告)号：US20140169440A1

公开(公告)日：2014-06-19

申请号：US13717973

申请日：2012-12-18

Applicant: LSI CORPORATION

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L27/01 ,  H04L27/00

CPC classification number: H04L25/063

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈回路中的控制器取消，以根据数据判定误差信号或用于停机恢复的定时信号产生补偿信号。

公开(公告)号：US09385858B2

公开(公告)日：2016-07-05

申请号：US13776905

申请日：2013-02-26

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L7/04 ,  H04L7/00

CPC classification number: H04L7/0004 ,  H04L7/007

Abstract: In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.

Abstract translation: 为了初始化在时钟和数据恢复（CDR）电路中使用的恢复时钟信号的相位，禁用正常的在线CDR处理。 模数转换器（ADC）采样的绝对值的总和是在ADC的模拟信号的每个单位间隔（UI）上为不同的时钟相位产生的，该模拟信号在指定的时间段内被采样。 选择对应于最大和的相位作为恢复的时钟信号的初始相位，用于启用的在线CDR处理，其中除了别的以外，还自动更新时钟相位，以确保ADC对模拟信号在中心附近进行采样 每个UI。

公开(公告)号：US09294313B2

公开(公告)日：2016-03-22

申请号：US14146920

申请日：2014-01-03

Applicant: LSI Corporation

Inventor： Tomasz Prokop ,  Volodmyr Shvydun ,  Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H03H7/30 ,  H03K5/159 ,  H04L25/03 ,  H03M9/00

CPC classification number: H04L25/03057 ,  H03M9/00 ,  H04L2025/03535

Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Abstract translation: 一种使用串联耦合信号处理块来处理数字化输入符号的串行器 - 解串器，每个块具有系数输入。 多个串联耦合系数延迟元件中的每一个具有控制输入，并且耦合到对应的一个信号处理模块的系数输入的系数输出由具有输入和多个输出的移位寄存器控制，每个 所述多个输出耦合到所述系数延迟元件中对应的一个的所述控制输入。 适配单元具有耦合到移位寄存器的输入的标志输出，以及耦合到系数延迟元件中的第一个的输入的第一系数输出。 当自适应单元生成系数时，适配单元生成标志，并且当移位寄存器接收到标志时，该系数被输入到系数延迟元件中的第一个。