公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US09524784B1

公开(公告)日：2016-12-20

申请号：US14848524

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.

Abstract translation: 本发明提供了用于控制对应于在非易失性存储器件的单元上执行功能的电压阈值分布的方法和相关联的器件。 在一个实施例中，提供了一种方法。 该方法可以包括提供非易失性存储器件。 该设备包括一个或多个字符串，每个字符串包括多个单元，多个单元包括第一单元和第二单元。 该方法还包括通过向第一单元施加第一功能电压和向第二单元施加第二功能电压来执行非易失性存储器件的功能。 第一功能电压和第二功能电压不同。

公开(公告)号：US09324431B1

公开(公告)日：2016-04-26

申请号：US14606647

申请日：2015-01-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/0466 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.

Abstract translation: 非易失性存储单元具有半导体衬底，包括浮置栅极上的电荷俘获层的多层堆叠，顶部导电层以及控制对非易失性存储单元的编程和擦除操作的电路。 编程和擦除操作使浮置栅极上的第一电荷密度比电荷俘获电介质层上的第二电荷密度更大。

公开(公告)号：US09018085B2

公开(公告)日：2015-04-28

申请号：US14198320

申请日：2014-03-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.

Abstract translation: 本发明的存储器件的制造方法至少包括以下步骤。 在衬底上形成隧道介电层。 在隧道电介质层上徘徊一扇门。 在栅极和隧道介电层之间形成至少一个电荷存储层。 在栅极旁边的衬底中形成两个掺杂区域。 字线形成在栅极上并电连接到栅极，其中字线的厚度大于栅极的厚度。

公开(公告)号：US11062759B1

公开(公告)日：2021-07-13

申请号：US16837041

申请日：2020-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Atsuhiro Suzuki ,  Yu-Hung Huang ,  Sheng-Kai Chen ,  Wen-Jer Tsai

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409 ,  G11C11/4076

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

公开(公告)号：US09786794B2

公开(公告)日：2017-10-10

申请号：US15096044

申请日：2016-04-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

公开(公告)号：US20160225911A1

公开(公告)日：2016-08-04

申请号：US15096044

申请日：2016-04-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US20140308791A1

公开(公告)日：2014-10-16

申请号：US14314830

申请日：2014-06-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 在该方法中，在基板上形成具有突出部的第一氧化物层。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和一对电荷存储间隔物上形成第二氧化物层。 导电层形成在第二氧化物层上，其中导电层完全位于一对电荷存储间隔物的顶部上。

公开(公告)号：US11289132B1

公开(公告)日：2022-03-29

申请号：US17168215

申请日：2021-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Chieh Cheng ,  Yin-Jen Chen

IPC: G11C7/00 ,  G11C11/00 ,  G11C5/14 ,  G11C8/08

Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.

公开(公告)号：US11037632B1

公开(公告)日：2021-06-15

申请号：US16828997

申请日：2020-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.