公开(公告)号：US09524784B1

公开(公告)日：2016-12-20

申请号：US14848524

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.

Abstract translation: 本发明提供了用于控制对应于在非易失性存储器件的单元上执行功能的电压阈值分布的方法和相关联的器件。 在一个实施例中，提供了一种方法。 该方法可以包括提供非易失性存储器件。 该设备包括一个或多个字符串，每个字符串包括多个单元，多个单元包括第一单元和第二单元。 该方法还包括通过向第一单元施加第一功能电压和向第二单元施加第二功能电压来执行非易失性存储器件的功能。 第一功能电压和第二功能电压不同。

公开(公告)号：US20170098478A1

公开(公告)日：2017-04-06

申请号：US14873486

申请日：2015-10-02

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C29/38 ,  G11C16/26 ,  G11C29/44 ,  G11C16/14

CPC classification number: G11C29/38 ,  G11C16/08 ,  G11C16/26 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/1202

Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.

公开(公告)号：US09437612B1

公开(公告)日：2016-09-06

申请号：US14832220

申请日：2015-08-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/16 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/7889 ,  H01L29/7926

Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.

Abstract translation: 三维存储器，其包括存储单元堆叠结构。 存储单元堆叠结构由多个存储单元阵列结构和绝缘层交替堆叠，并且每个存储单元阵列结构包括字线，有源层，复合层和源极/漏极。 字线，有源层和复合层沿Y方向延伸。 有源层设置在相邻字线之间。 复合层设置在相邻字线和相邻有源层之间，并且每个复合层从有源层依次包括第一介电层，电荷存储层和第二介质层。 源/排水口以相等的间隔设置在活性层中。 存储单元包括两个相邻的源/漏极，两个相邻源极/漏极之间的有源层，有源层上的第一介电层，电荷存储层和第二介电层以及字线。

公开(公告)号：US09589982B1

公开(公告)日：2017-03-07

申请号：US14854383

申请日：2015-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

Abstract translation: 本发明的实施例提供改进的三维存储器单元，阵列，器件和/或类似物以及相关联的方法。 在一个实施例中，提供三维存储单元。 三维存储单元包括第一导电层; 与所述第一导电层间隔开的第三导电层; 连接第一导电层和第三导电层以形成具有内表面的开口的沟道导电层; 沿着由所述第一导电层，所述沟道导电层和所述第三导电层包围的所述开口的内表面设置的电介质层; 以及插入并基本上填充由电介质层形成的剩余开口部分的第二导电层。 第一导电层，电介质层和第二导电层被配置成形成阶梯结构。

公开(公告)号：US20160336339A1

公开(公告)日：2016-11-17

申请号：US14881350

申请日：2015-10-13

Applicant: Macronix International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L27/115 ,  G11C16/14 ,  H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C2216/02 ,  H01L27/11565 ,  H01L29/7926

Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.

Abstract translation: 本发明的实施例提供改进的3D非易失性存储器件和相关联的方法。 在一个实施例中，提供一串3D非易失性存储单元。 弦线包括沿着弦的轴线延伸的芯，芯在垂直于轴线的平面中具有椭圆形横截面; 以及多个字线，每个字线围绕所述芯的一部分设置，所述多个字线沿着所述轴间隔开，并且每个字线对应于所述存储器单元之一。 在各种实施例中，为了改善3D非易失性存储器件的操作，定义了至少一个操作参数。