公开(公告)号：US20160020295A1

公开(公告)日：2016-01-21

申请号：US14334325

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Chih Chen ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L29/45 ,  H01L29/16 ,  H01L21/283 ,  H01L29/04

CPC classification number: H01L21/76889 ,  H01L21/26506 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在半导体中形成硅化物区域。 该方法可以允许具有改善的电阻和减少的硅化物桥形成的具有硅化物层的半导体。

公开(公告)号：US09741607B2

公开(公告)日：2017-08-22

申请号：US15351774

申请日：2016-11-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Zheng-Chang Mu ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0361 ,  H01L2224/05089 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

公开(公告)号：US11183513B1

公开(公告)日：2021-11-23

申请号：US16865442

申请日：2020-05-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jr-Meng Wang ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

公开(公告)号：US20180294276A1

公开(公告)日：2018-10-11

申请号：US15483019

申请日：2017-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuan-Cheng Liu ,  Yu-Lin Liu ,  Cheng-Wei Lin ,  Chin-Cheng Yang ,  Shou-Wei Huang

IPC: H01L27/11582 ,  H01L23/544 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

公开(公告)号：US09536808B1

公开(公告)日：2017-01-03

申请号：US14741087

申请日：2015-06-16

Applicant: Macronix International Co., Ltd.

Inventor： Zheng-Chang Mu ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0361 ,  H01L2224/05089 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract translation: 提供具有大通孔（例如焊盘下方）的半导体器件，以增加通孔开口面积比，增加通孔蚀刻速率，避免金属间电介质破裂和对集成电路的损坏。 通孔被定义为在隔离的导电底部基底层和导电顶层之间的金属间介电层中的大的开放区域。 还提供了制造具有大通孔的半导体器件的方法。

公开(公告)号：US20160247719A1

公开(公告)日：2016-08-25

申请号：US15146187

申请日：2016-05-04

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Chih Chen ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L29/792 ,  H01L21/28 ,  H01L23/532

CPC classification number: H01L21/76889 ,  H01L21/26506 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在半导体中形成硅化物区域。 该方法可以允许具有改善的电阻和减少的硅化物桥形成的具有硅化物层的半导体。

公开(公告)号：US10103166B1

公开(公告)日：2018-10-16

申请号：US15483019

申请日：2017-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuan-Cheng Liu ,  Yu-Lin Liu ,  Cheng-Wei Lin ,  Chin-Cheng Yang ,  Shou-Wei Huang

IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/544 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.