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公开(公告)号：US11025256B2
公开(公告)日：2021-06-01
申请号：US16435568
申请日：2019-06-10
Applicant: MEDIATEK INC.
Inventor： Yi-Chieh Huang , Sung-Lin Tsai
Abstract: A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.
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公开(公告)号：US20200067515A1
公开(公告)日：2020-02-27
申请号：US16435568
申请日：2019-06-10
Applicant: MEDIATEK INC.
Inventor： Yi-Chieh Huang , Sung-Lin Tsai
Abstract: A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.
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3.发明申请METHOD FOR PERFORMING PHASE SHIFT CONTROL FOR TIMING RECOVERY IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS 有权用于执行电子设备中的时序恢复的相位移动控制的方法及相关装置公开(公告)号：US20160308665A1
公开(公告)日：2016-10-20
申请号：US15194509
申请日：2016-06-27
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Bo-Jiun Chen , Ke-Chung Wu , Yi-Chieh Huang
CPC classification number: H04L7/0087 , H03F3/45475 , H03K3/0322 , H03K5/131 , H03K2005/00052 , H03K2005/00058 , H03L7/0807 , H03L7/0814 , H04L7/0331
Abstract: A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.
Abstract translation: 提供一种用于执行电子设备和相关设备中的定时恢复的相移控制的方法，其中该方法包括：产生振荡器的输出信号，其中通过选择性地组合来控制振荡器的输出信号的相移 根据一组数字控制信号将一组时钟信号输入到振荡器中，并且从时钟发生器获得该组时钟信号，其中相移对应于该组数字控制信号，并且该组数字控制信号 携带一组数字加权，用于选择性地混合该组时钟信号; 并根据振荡器的输出信号在电子设备中的接收机的接收机输入信号上执行定时恢复和采样，以从接收机输入信号再现数据。
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公开(公告)号：US20160211967A1
公开(公告)日：2016-07-21
申请号：US14943129
申请日：2015-11-17
Applicant: MEDIATEK Inc.
Inventor： Yi-Chieh Huang , Ping-Ying Wang
CPC classification number: H03L7/1976 , H03C3/00 , H03C3/0933
Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.
Abstract translation: 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。
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5.发明授权Supply voltage drift insensitive digitally controlled oscillator and phase locked loop circuit 有权电源电压漂移不敏感数字控制振荡器和锁相环电路公开(公告)号：US09306577B2
公开(公告)日：2016-04-05
申请号：US13778935
申请日：2013-02-27
Applicant: MediaTek Inc.
Inventor： Yi-Chieh Huang , Ping-Ying Wang
CPC classification number: H03L1/00 , H03K3/0315 , H03L7/0995 , H03L7/14 , H03L2207/06 , H03L2207/08
Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.
Abstract translation: 数字控制振荡器包括环形振荡器和第一辅助电路。 环形振荡器耦合到电源电压并产生以振荡频率振荡的信号。 振荡频率由数字代码控制，并进一步随第一方向的电源电压漂移而变化。 第一辅助电路耦合到环形振荡器，并且促使振荡频率随着与第一方向相反的第二方向上的电源电压漂移而变化。
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Patent Agency Ranking
公开(公告)号：US09634677B2
公开(公告)日：2017-04-25
申请号：US15052183
申请日：2016-02-24
Applicant: MediaTek Inc.
Inventor： Yi-Chieh Huang
Abstract: A control technique for an injection-locked phase-locked loop (ILPLL) includes the following steps: providing the ILPLL with a sampling clock and an injection clock for an integral path and a proportional path of the ILPLL, respectively; making a change in the power level of the injection clock to get the phase error of the integral path of the ILPLL; and controlling the phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the ILPLL.
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公开(公告)号：US09654116B1
公开(公告)日：2017-05-16
申请号：US15261884
申请日：2016-09-10
Applicant: MEDIATEK INC.
Inventor： Yi-Chieh Huang
CPC classification number: H03L7/083 , H03K3/0315 , H03L7/0995
Abstract: A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.
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公开(公告)号：US09608798B2
公开(公告)日：2017-03-28
申请号：US15194509
申请日：2016-06-27
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Bo-Jiun Chen , Ke-Chung Wu , Yi-Chieh Huang
CPC classification number: H04L7/0087 , H03F3/45475 , H03K3/0322 , H03K5/131 , H03K2005/00052 , H03K2005/00058 , H03L7/0807 , H03L7/0814 , H04L7/0331
Abstract: A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.
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公开(公告)号：US20170117904A1
公开(公告)日：2017-04-27
申请号：US15261884
申请日：2016-09-10
Applicant: MEDIATEK INC.
Inventor： Yi-Chieh Huang
CPC classification number: H03L7/083 , H03K3/0315 , H03L7/0995
Abstract: A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.
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10.发明授权公开(公告)号：US09584143B2
公开(公告)日：2017-02-28
申请号：US14943129
申请日：2015-11-17
Applicant: MEDIATEK Inc.
Inventor： Yi-Chieh Huang , Ping-Ying Wang
CPC classification number: H03L7/1976 , H03C3/00 , H03C3/0933
Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.
Abstract translation: 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。
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