-
公开(公告)号：US11768782B2
公开(公告)日：2023-09-26
申请号：US17880226
申请日：2022-08-03
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Ali Feiz Zarrin Ghalam , Chin-Yu Chen , Jongin Kim
IPC: G06F13/16 , G11C16/32 , H03K3/017 , G11C29/02 , G11C29/12 , G11C29/16 , G11C7/22 , H03K5/156 , G11C16/04
CPC classification number: G06F13/1668 , G11C16/32 , H03K3/017 , G11C16/0483
Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.
-
公开(公告)号：US20230289307A1
公开(公告)日：2023-09-14
申请号：US18119578
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
CPC classification number: G06F13/30 , G06F13/1668
Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.
-
公开(公告)号：US11079946B2
公开(公告)日：2021-08-03
申请号：US16171442
申请日：2018-10-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Ali Feiz Zarrin Ghalam , Guan Wang , Qiang Tang
Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
-
公开(公告)号：US10911033B2
公开(公告)日：2021-02-02
申请号：US16392352
申请日：2019-04-23
Applicant: Micron Technology, Inc.
Inventor： Ali Feiz Zarrin Ghalam , Luigi Pilolli , Myung Gyoo Won
IPC: H03K3/017 , H03K19/0185 , H03K3/356
Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.
-
公开(公告)号：US10658041B1
公开(公告)日：2020-05-19
申请号：US16205755
申请日：2018-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Agatino Massimo Maccarrone , Hoon Choi , Qiang Tang , Ali Feiz Zarrin Ghalam
Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.
-
Patent Agency Ranking
公开(公告)号：US20190295614A1
公开(公告)日：2019-09-26
申请号：US16429209
申请日：2019-06-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kaveh Shakeri , Ali Feiz Zarrin Ghalam , Qiang Tang , Eric N. Lee
Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.
-
公开(公告)号：US20190180802A1
公开(公告)日：2019-06-13
申请号：US15834315
申请日：2017-12-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kaveh Shakeri , Ali Feiz Zarrin Ghalam
CPC classification number: G11C7/222 , G11C7/1039 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1093 , G11C8/04 , G11C8/06 , G11C8/18 , G11C16/0483
Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.
-
公开(公告)号：US10270429B1
公开(公告)日：2019-04-23
申请号：US15848796
申请日：2017-12-20
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Qiang Tang , Ali Feiz Zarrin Ghalam
Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
-
公开(公告)号：US20170285938A1
公开(公告)日：2017-10-05
申请号：US15084979
申请日：2016-03-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Eric Lee , Qiang Tang , Ali Feiz Zarrin Ghalam , Hoon Choi , Daesik Song
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0802 , G06F2212/222 , G06F2212/7203 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C16/26 , G11C16/32
Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.
-
公开(公告)号：US09401188B2
公开(公告)日：2016-07-26
申请号：US14216528
申请日：2014-03-17
Applicant: Micron Technology, Inc.
Inventor： Toru Tanzawa , Ali Feiz Zarrin Ghalam
CPC classification number: G11C7/22 , G11C5/143 , G11C7/1066 , G11C7/1087 , G11C7/1093
Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.
Abstract translation: 描述包括使能电路的设备和系统的示例。 可以使用两个电压源来操作设备的不同部分，包括外围电路和I / O电路。 当一个或多个器件的外围电路的电源被禁止时，该器件的I / O电路可能被禁止。 在一些示例中，可以通过消除或减少通过I / O电路的DC电流路径来部分地节省功率。
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.021 seconds)
