公开(公告)号：US10998031B2

公开(公告)日：2021-05-04

申请号：US16569588

申请日：2019-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C7/02 ,  G11C11/22 ,  H01L27/11507 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509 ,  G11C11/56

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US10896717B2

公开(公告)日：2021-01-19

申请号：US16235163

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C5/14 ,  G11C11/4074 ,  G06F3/06

Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.

公开(公告)号：US10783948B2

公开(公告)日：2020-09-22

申请号：US16425769

申请日：2019-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11502

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US10127972B2

公开(公告)日：2018-11-13

申请号：US15679042

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US10074414B2

公开(公告)日：2018-09-11

申请号：US15679016

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11509 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US20180061477A1

公开(公告)日：2018-03-01

申请号：US15679042

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C8/16 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  H01L27/108

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/06 ,  G11C7/062 ,  G11C7/18 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/108 ,  H01L27/10897

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20180061468A1

公开(公告)日：2018-03-01

申请号：US15678978

申请日：2017-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11502

CPC classification number: G11C11/221 ,  G11C11/2253 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11514 ,  H01L28/55 ,  H01L28/90

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US11967362B2

公开(公告)日：2024-04-23

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C16/04 ,  G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US20230395130A1

公开(公告)日：2023-12-07

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US11706909B2

公开(公告)日：2023-07-18

申请号：US17083174

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mitsunari Sukekawa ,  Yusuke Yamamoto ,  Christopher J. Kawamura ,  Hiroaki Taketani

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/31 ,  H01L23/5283 ,  H10B12/033 ,  H10B12/05 ,  H10B12/488

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.