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公开(公告)号：US10134481B2
公开(公告)日：2018-11-20
申请号：US15449426
申请日：2017-03-03
发明人： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
摘要： Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
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公开(公告)号：US09589659B1
公开(公告)日：2017-03-07
申请号：US15164171
申请日：2016-05-25
发明人： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5621 , G11C2211/5648
摘要： Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
摘要翻译： 操作存储器的方法包括将要编程的第一存储器单元的多个可能数据状态的第一目标数据状态存储在耦合到数据节点的目标数据锁存器中，存储多个第二目标数据状态的至少一位 要在与数据节点耦合的攻击者数据锁存器中编程的第二存储器单元的可能数据状态，以及编程第一存储器单元并对第一目标数据状态执行程序验证操作，以确定第一存储器单元是否被验证 第一个目标数据状态。 所述程序验证操作包括：基于存储在所述侵入者数据锁存器中的所述第二目标状态的所述至少一个位，执行所述中间验证时，对应于所述攻击量的中间验证以向所述数据节点施加电压; 以及基于存储在侵略者数据锁存器中的第二目标状态的至少一个位，在执行程序验证时，对应于不侵略条件的程序验证应用于数据节点的电压。 所述方法包括如果在中间验证期间验证第一存储器单元并且侵略者数据锁存器中的至少一个位对应于特定的侵略量，则禁止第一存储器单元进一步编程，或者在第一存储器单元期间验证第一存储器单元 程序验证，并且攻击者数据锁存中的至少一个位对应于无侵略的条件。 第二存储器单元是第一存储器单元的邻居。
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公开(公告)号：US20240233825A9
公开(公告)日：2024-07-11
申请号：US18489454
申请日：2023-10-18
发明人： Federica Paolini , Violante Moschiano , Marco Domenico Tiburzi , Leo Raimondo , Filippo Bruno , Shigekazu Yamada
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/30
摘要： A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
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公开(公告)号：US20240135994A1
公开(公告)日：2024-04-25
申请号：US18489454
申请日：2023-10-17
发明人： Federica Paolini , Violante Moschiano , Marco Domenico Tiburzi , Leo Raimondo , Filippo Bruno , Shigekazu Yamada
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/30
摘要： A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
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公开(公告)号：US20230134281A1
公开(公告)日：2023-05-04
申请号：US17976423
申请日：2022-10-28
发明人： Leo Raimondo , Federica Paolini , Umberto Siciliani , Violante Moschiano , Gianfranco Valeri , Davide Esposito , Walter Di Francesco
摘要： A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.
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公开(公告)号：US20170345511A1
公开(公告)日：2017-11-30
申请号：US15449426
申请日：2017-03-03
发明人： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5621 , G11C2211/5648
摘要： Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
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