公开(公告)号：US12256543B2

公开(公告)日：2025-03-18

申请号：US17669039

申请日：2022-02-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Ya-Chun Tsai

IPC: H01L29/76 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10D30/67

Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.

公开(公告)号：US20230255028A1

公开(公告)日：2023-08-10

申请号：US17669039

申请日：2022-02-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Ya-Chun Tsai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/5283 ,  H01L29/42392

Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.

公开(公告)号：US20230255027A1

公开(公告)日：2023-08-10

申请号：US17669016

申请日：2022-02-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting

IPC: H01L27/11582 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526 ,  H01L23/5283

Abstract: A memory device includes a substrate, a plurality of first memory arrays, a plurality of first bit lines, a first common source plate, and a first through-array contact. The plurality of first memory arrays are disposed in a first plane region of the substrate. The plurality of first bit lines are located between the plurality of first memory arrays and the substrate and are electrically connected to the plurality of first memory arrays. The first common source plate is located above the plurality of first memory arrays and is electrically connected to the plurality of first memory arrays. The first through-array contact is disposed in a first contact region outside the first plane region and is electrically connected to the first common source plate.

公开(公告)号：US12200925B2

公开(公告)日：2025-01-14

申请号：US17723965

申请日：2022-04-19

Applicant: Macronix International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Chih-Ting Hu

IPC: H10B41/23 ,  H10B41/41

Abstract: Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

公开(公告)号：US20240105239A1

公开(公告)日：2024-03-28

申请号：US17953094

申请日：2022-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  I-Chen Yang

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1057 ,  G11C7/067 ,  G11C7/12

Abstract: A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

公开(公告)号：US11031509B1

公开(公告)日：2021-06-08

申请号：US16842788

申请日：2020-04-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28

Abstract: A memory device including a substrate, a stack structure, an isolation structure, an inter-gate dielectric layer, a control gate, a first insulation structure, a first gate dielectric layer, and a first gate. The stack structure is disposed on the substrate. The isolation structure is disposed in the substrate and disposed at two sides of the stack structure. The inter-gate dielectric layer covers the stack structure and the isolation structure. The control gate covers the inter-gate dielectric layer. The first insulation structure is disposed in the substrate, wherein a top surface of the first insulation structure is lower than a top surface of the substrate, so that a side surface of a portion of the substrate is exposed. The first gate dielectric layer is disposed on the top surface and the side surface of the substrate. The first gate covers the first gate dielectric layer.

公开(公告)号：US20250107106A1

公开(公告)日：2025-03-27

申请号：US18471295

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A memory device includes a substrate, a bonding structure and bit lines. The substrate includes adjacent first and second regions. The bonding structure is over the substrate and includes a bonding dielectric layer and first and second bonding pads. The bonding dielectric layer is over the substrate in the first and the second regions. The first and second bonding pads are respectively embedded in the bonding dielectric layer over the substrate in the first and second regions. The bit lines are over the bonding structure and extend from the first region to the second region. A density of the first bonding pads in the first region is greater than a density of the second bonding pads in the second region. The memory device may be 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US12176058B2

公开(公告)日：2024-12-24

申请号：US17953094

申请日：2022-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  I-Chen Yang

IPC: G11C16/14 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C16/16

Abstract: A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

公开(公告)号：US20230337421A1

公开(公告)日：2023-10-19

申请号：US17723965

申请日：2022-04-19

Applicant: Macronix International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Chih-Ting Hu

IPC: H01L27/11553 ,  H01L27/11529

CPC classification number: H01L27/11553 ,  H01L27/11529

Abstract: Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.