公开(公告)号：US20240332229A1

公开(公告)日：2024-10-03

申请号：US18619071

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Tzu Ching Hung ,  Kyle K. Kirby ,  Julia VanWinkle ,  Kyle B. Campbell ,  Bret K. Street

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/06517 ,  H01L2224/08146

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

公开(公告)号：US20230395545A1

公开(公告)日：2023-12-07

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0652 ,  H01L24/80 ,  H01L24/95 ,  H01L2224/80047 ,  H01L2224/8001 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/08148 ,  H01L2224/95093 ,  H01L2224/80204 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/182 ,  H01L2924/1011

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US20210375902A1

公开(公告)日：2021-12-02

申请号：US17396952

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  David Daycock ,  Subramanian Krishnan ,  Leroy Ekarista Wibowo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11526

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material. The first and second insulator materials comprise different compositions relative one another. Conductive vias are formed in the second insulator material that are individually directly electrically coupled to the individual channel-material strings through the upwardly-projecting conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210151454A1

公开(公告)日：2021-05-20

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US11876068B2

公开(公告)日：2024-01-16

申请号：US17956797

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/49 ,  H01L24/06 ,  H01L25/18 ,  H01L2924/15165

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US11502053B2

公开(公告)日：2022-11-15

申请号：US17103834

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US20220328456A1

公开(公告)日：2022-10-13

申请号：US17850992

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

公开(公告)号：US20220165708A1

公开(公告)日：2022-05-26

申请号：US17103486

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

公开(公告)号：US20250140753A1

公开(公告)日：2025-05-01

申请号：US18920749

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.

公开(公告)号：US20250118693A1

公开(公告)日：2025-04-10

申请号：US18776197

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. A semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.