公开(公告)号：US20250094344A1

公开(公告)日：2025-03-20

申请号：US18782380

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250069680A1

公开(公告)日：2025-02-27

申请号：US18949086

申请日：2024-11-15

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/4093

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US20250028486A1

公开(公告)日：2025-01-23

申请号：US18803440

申请日：2024-08-13

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.

公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US12148498B2

公开(公告)日：2024-11-19

申请号：US17959191

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C11/406 ,  G11C11/4093 ,  G11C29/52

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US12079509B2

公开(公告)日：2024-09-03

申请号：US17868286

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F3/06 ,  G06F3/00 ,  G06F11/00 ,  G06F11/10

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1048

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

公开(公告)号：US20230367575A1

公开(公告)日：2023-11-16

申请号：US17744350

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Niccolo Izzo ,  Alessandro Orlando ,  Danilo Caraccio ,  David Hulton

IPC: G06F8/65 ,  H04L9/08

CPC classification number: G06F8/65 ,  H04L9/088

Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.

公开(公告)号：US11740837B2

公开(公告)日：2023-08-29

申请号：US17856556

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Nicola Colella ,  Danilo Caraccio ,  Alessandro Orlando

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0646 ,  G06F2212/657

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

公开(公告)号：US11663062B2

公开(公告)日：2023-05-30

申请号：US17668210

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/30 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/3037

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US20220357791A1

公开(公告)日：2022-11-10

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.