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公开(公告)号：US10783965B2
公开(公告)日：2020-09-22
申请号：US16399144
申请日：2019-04-30
发明人： DerChang Kau , Gianpaolo Spadini
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20190259453A1
公开(公告)日：2019-08-22
申请号：US16399144
申请日：2019-04-30
发明人： DerChang Kau , Gianpaolo Spadini
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US10304534B2
公开(公告)日：2019-05-28
申请号：US16198347
申请日：2018-11-21
发明人： DerChang Kau , Gianpaolo Spadini
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20190013358A1
公开(公告)日：2019-01-10
申请号：US16045514
申请日：2018-07-25
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US09514809B2
公开(公告)日：2016-12-06
申请号：US14808385
申请日：2015-07-24
发明人： Jong Won Lee , Gianpaolo Spadini
摘要： Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.
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6.发明授权公开(公告)号：US09368554B2
公开(公告)日：2016-06-14
申请号：US14973446
申请日：2015-12-17
发明人： DerChang Kau , Gianpaolo Spadini
IPC分类号： G11C11/00 , H01L27/24 , H01L45/00 , H01L23/528
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
摘要翻译： 一些实施例包括具有存储器单元，被配置为访问存储单元的第一和第二导线以及被配置为向第一和第二导线中的一个施加信号的开关的装置和方法。 在这样的实施例中的至少一个中，开关可以包括相变材料。 描述包括附加装置和方法的其他实施例。
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公开(公告)号：US20190096484A1
公开(公告)日：2019-03-28
申请号：US16198347
申请日：2018-11-21
发明人： DerChang Kau , Gianpaolo Spadini
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US09659997B2
公开(公告)日：2017-05-23
申请号：US15058810
申请日：2016-03-02
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US20160104747A1
公开(公告)日：2016-04-14
申请号：US14973446
申请日：2015-12-17
发明人： DerChang Kau , Gianpaolo Spadini
IPC分类号： H01L27/24 , H01L23/528 , H01L45/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20150332762A1
公开(公告)日：2015-11-19
申请号：US14808385
申请日：2015-07-24
发明人： Jong Won Lee , Gianpaolo Spadini
IPC分类号： G11C13/00
CPC分类号： G11C13/0023 , G11C5/025 , G11C8/12 , G11C11/1653 , G11C11/1659 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71
摘要： Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.
摘要翻译： 提供了存储器阵列及其形成方法。 示例性存储器阵列可以包括具有以矩阵形式布置的多个存储单元和多个平面选择装置的至少一个平面。 多个存储器单元的组通信地耦合到多个平面选择装置中的相应一个。 具有元件的解码逻辑形成在衬底材料中并且通信地耦合到多个平面选择装置。 多个存储单元和多个平面选择装置不形成在基板材料中。
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