公开(公告)号：US20240063168A1

公开(公告)日：2024-02-22

申请号：US17889170

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： See Hiong Leow ,  Hong Wan NG ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Ling Pan

IPC: H01L23/00 ,  H01L27/105

CPC classification number: H01L24/48 ,  H01L27/1052 ,  H01L2224/48105

Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

公开(公告)号：US20240282751A1

公开(公告)日：2024-08-22

申请号：US18440444

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Hong Wan Ng ,  See Hiong Leow ,  Chong C. Hui

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/48132 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/3511

Abstract: A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.

公开(公告)号：US20240194547A1

公开(公告)日：2024-06-13

申请号：US18517980

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Seng Kim Ye ,  Hong Wan Ng ,  Kelvin Aik Boo Tan ,  See Hiong Leow

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/48 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265

Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.

公开(公告)号：US20240071886A1

公开(公告)日：2024-02-29

申请号：US17823349

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/35121

Abstract: Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.