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公开(公告)号：US20250028373A1
公开(公告)日：2025-01-23
申请号：US18773178
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Leonid Minz , Sivagnanam Parthasarathy
Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.
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公开(公告)号：US12164375B2
公开(公告)日：2024-12-10
申请号：US17949655
申请日：2022-09-21
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Fan Zhou
IPC: G06F11/10 , G06F7/501 , G06F11/07 , G11C29/44 , G11C29/52 , H03M13/11 , H03M13/15 , H03M13/29 , H03M13/37 , H03M13/45
Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
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公开(公告)号：US12088301B2
公开(公告)日：2024-09-10
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US20240185898A1
公开(公告)日：2024-06-06
申请号：US18523366
申请日：2023-11-29
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Leon Zlotnik , Yoav Weinberg
CPC classification number: G11C7/1012 , G06F11/1068 , G11C7/1039
Abstract: A method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. The method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.
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公开(公告)号：US20240020223A1
公开(公告)日：2024-01-18
申请号：US17867375
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
CPC classification number: G06F12/023 , G06F9/5016 , G06F12/0292
Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address of the memory resource nor a last physical address of the memory resource. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address of the memory resource. In contrast, in response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address of the memory resource.
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Patent Agency Ranking
公开(公告)号：US11747842B1
公开(公告)日：2023-09-05
申请号：US17717599
申请日：2022-04-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Aspects of the present disclosure are directed to multi-referenced power supplies. One method includes sensing each voltage, via a voltage sensor, of plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor, and selecting a feedback voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages.
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公开(公告)号：US20250155910A1
公开(公告)日：2025-05-15
申请号：US18917386
申请日：2024-10-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Ekram H. Bhuiyan
Abstract: Control circuitry is coupled to a first voltage regulation circuit and a second voltage regulation circuit. The control circuitry determines that a signal criterion has been met and controls application of a voltage signal generated by the second voltage regulation circuit to stabilize a voltage signal generated by the first voltage regulation circuit. The signal criterion is associated with a current level of a current flowing on a power line input to the first voltage regulation circuit, the second voltage regulation circuit, or both.
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公开(公告)号：US20250105829A1
公开(公告)日：2025-03-27
申请号：US18789278
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the SoC, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
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公开(公告)号：US20250104794A1
公开(公告)日：2025-03-27
申请号：US18975645
申请日：2024-12-10
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.
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公开(公告)号：US20250103088A1
公开(公告)日：2025-03-27
申请号：US18789228
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F1/06
Abstract: Voltage sensing circuitry and management circuitry provide voltage and clock frequency management. The voltage sensing circuitry may be configured to detect a voltage associated with a system-on-chip (SoC) and determine when the voltage transitions from a first voltage to a second voltage. The management circuitry may be configured to generate clocking signals for the SoC and alter a frequency of the generated clocking signals in response to the detected voltage transition.
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