公开(公告)号：US20250013364A1

公开(公告)日：2025-01-09

申请号：US18896573

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F11/34 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/0893

Abstract: Memory devices are disclosed. A memory device may include hybrid cache including single-level cell (SLC) blocks of memory and non-SLC blocks of memory. The memory device may further include a memory controller configured to disable, based on workload of the hybrid cache, a portion of the hybrid cache such that writes are only directed to another, different portion of the cache. Associated methods and systems are also disclosed.

公开(公告)号：US20240363190A1

公开(公告)日：2024-10-31

申请号：US18771393

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

公开(公告)号：US11721404B2

公开(公告)日：2023-08-08

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/349 ,  G11C16/12 ,  G11C2211/5641

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11715541B2

公开(公告)日：2023-08-01

申请号：US17867538

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10 ,  G06F11/07 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/10 ,  G06F11/076 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/1048 ,  G11C29/52

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

公开(公告)号：US20230076362A1

公开(公告)日：2023-03-09

申请号：US17984929

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, JR. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US11456051B1

公开(公告)日：2022-09-27

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C16/10 ,  G11C29/50

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220199179A1

公开(公告)日：2022-06-23

申请号：US17127012

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

公开(公告)号：US11366592B2

公开(公告)日：2022-06-21

申请号：US17007539

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besigna

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US20220066650A1

公开(公告)日：2022-03-03

申请号：US17007539

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besinga

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US11204696B2

公开(公告)日：2021-12-21

申请号：US16396432

申请日：2019-04-26

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0888 ,  G06F11/34 ,  G06F12/0893

Abstract: Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points. A method of operating a memory device may include writing data in the static cache if the static cache is available, and writing the data in the dynamic cache if the static cache is unavailable.