公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC: G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract translation: 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

公开(公告)号：US20140337659A1

公开(公告)日：2014-11-13

申请号：US13892931

申请日：2013-05-13

Applicant: Nvidia Corporation

Inventor： Guillermo J. Rozas ,  Jason Golbus ,  Chi Keung Lee

IPC: G06F1/08

CPC classification number: G06F1/12

Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.

Abstract translation: 双域动态多路复用器和在异步电压和频域之间转换的方法。 双域动态多路复用器的一个实施例包括：（1）具有第一电压和第一时钟的第一域，以及具有第二电压和第二时钟的第二域，（2）多个数据和数据选择输入 对，其中输入对的数据输入处于第一域，并且输入对的数据选择输入处于第二域，以及（3）第二域中的预充电阶段，其在 第二时钟，由此一个数据和数据输入对被使能，并且数据在第二时钟的另一边缘被锁存在第二域中。

公开(公告)号：US20240296875A1

公开(公告)日：2024-09-05

申请号：US18176836

申请日：2023-03-01

Applicant: NVIDIA Corporation

Inventor： Jason Golbus ,  Chad Parsons ,  Kirk Twardowski ,  Lalit Gupta ,  Jesse Wang ,  Ka Yun Lee ,  Amy Chen ,  Ramya Challa ,  Karan Gupta

IPC: G11C7/10 ,  G11C29/50

CPC classification number: G11C7/1048 ,  G11C7/1075 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/5004

Abstract: The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.

公开(公告)号：US10234893B2

公开(公告)日：2019-03-19

申请号：US13892931

申请日：2013-05-13

Applicant: Nvidia Corporation

Inventor： Guillermo J Rozas ,  Jason Golbus ,  Chi Keung Lee

IPC: G06F1/12

Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.