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    SCALABLE HIGH-VOLTAGE CONTROL CIRCUITS USING THIN FILM ELECTRONICS
    4.
    发明申请
    SCALABLE HIGH-VOLTAGE CONTROL CIRCUITS USING THIN FILM ELECTRONICS 有权

    公开(公告)号：US20220293796A1

    公开(公告)日：2022-09-15

    申请号：US17196354

    申请日：2021-03-09

    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED

    Inventor： Jengping Lu

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/40

    Abstract: A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor serves as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor serves as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor.

    POLARIZATION CONTROLLED TRANSISTOR
    5.
    发明申请
    POLARIZATION CONTROLLED TRANSISTOR 有权

    公开(公告)号：US20220005938A1

    公开(公告)日：2022-01-06

    申请号：US16920249

    申请日：2020-07-02

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Thomas Wunderer ,  Jengping Lu ,  Noble M. Johnson

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

    Abstract: A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.

    Transparent optical coupler active matrix array
    7.
    发明授权
    Transparent optical coupler active matrix array 有权

    公开(公告)号：US10397529B2

    公开(公告)日：2019-08-27

    申请号：US15582296

    申请日：2017-04-28

    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED

    Inventor： Jengping Lu ,  Patrick Y. Maeda ,  Sourobh Raychaudhuri ,  David K. Biegelsen ,  Eugene M. Chow

    IPC: H01L27/12 ,  H04N5/33 ,  H04N9/04 ,  H01L31/112 ,  G02B27/14 ,  G01N21/88 ,  G02B27/60

    Abstract: A backplane has an array of output terminals arranged on an output surface of the backplane, and an array of solid state optical switches, each optical switch corresponding to one of the output terminals, wherein the solid state optical switches are responsive to light of a control wavelength and are transparent to light of a sensing wavelength, wherein the backplane is of a material transparent to light of a sensing wavelength different from the control wavelength. An optical system includes a backplane having an array of optocouplers, a projector to generate light of a control wavelength to which the optocouplers are responsive, optics to direct the control light onto the array of optocouplers on a backplane, an imaging system responsive to light of a sensing wavelength, wherein the backplane is at least partially transparent to the sensing wavelength.

    Gated co-planar poly-silicon thin film diode
    8.
    发明授权
    Gated co-planar poly-silicon thin film diode 有权
    门式共面多晶硅薄膜二极管

    公开(公告)号：US08871548B2

    公开(公告)日：2014-10-28

    申请号：US13770785

    申请日：2013-02-19

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Jengping Lu ,  Raj B. Apte

    IPC: H01L21/00 ,  H01L29/66 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20

    CPC classification number: H01L29/66477 ,  H01L29/04 ,  H01L29/1604 ,  H01L29/20 ,  H01L29/66356 ,  H01L29/7391

    Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate.

    Abstract translation: 二极管具有第一导电类型的材料的第一接触，与第一接触面共面布置的具有第二导电类型的材料的第二接触，在第一和第二接触之间共面布置的沟道，栅极 布置在所述通道附近，以及电连接到所述栅极的电压源。 二极管具有布置在衬底上的材料层，第一掺杂材料区域具有第一导电类型，掺杂第二导电类型的第二材料区域，由未掺杂的第一和第二区域形成的沟道 区域，邻近沟道布置的栅极和电连接到栅极的电压源。 一种方法包括在衬底上形成材料层，在材料中形成第一导电性的第一区域，在材料中形成第二导电性的第二区域，其布置成在第一和第二区域之间提供沟道区域 ，沟道区域保留未掺杂，在该材料层上沉积一层栅极电介质，在栅极电介质上布置与该沟道区相邻的栅极，以及将电压源电连接至该栅极。

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