公开(公告)号：US08673730B2

公开(公告)日：2014-03-18

申请号：US13301255

申请日：2011-11-21

申请人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

发明人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

IPC分类号： H01L21/20

CPC分类号： H01L28/92 ,  H01L27/1085

摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。

公开(公告)号：US20130146561A1

公开(公告)日：2013-06-13

申请号：US13313566

申请日：2011-12-07

申请人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

发明人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

IPC分类号： B05D5/12

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。

公开(公告)号：US08613861B2

公开(公告)日：2013-12-24

申请号：US13313566

申请日：2011-12-07

申请人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

发明人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

IPC分类号： H01B13/00

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。

公开(公告)号：US08048762B2

公开(公告)日：2011-11-01

申请号：US12546938

申请日：2009-08-25

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L21/76

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/24

摘要： A manufacturing method for a semiconductor device includes: forming a first layer on a member to be etched; forming a first hard mask that includes a first hard mask pattern, in the first layer; forming a second layer on the first hard mask and on an exposed surface of the member to be etched; removing by selective etching the second layer to form a side wall core that includes a core pattern; forming side wall spacers on side walls of the side wall core; and using the side wall spacers and the first hard mask to remove by etching the member to be etched.

摘要翻译： 半导体器件的制造方法包括：在要蚀刻的部件上形成第一层; 在第一层中形成包括第一硬掩模图案的第一硬掩模; 在第一硬掩模上和待蚀刻部件的暴露表面上形成第二层; 通过选择性蚀刻第二层以形成包括芯图案的侧壁芯; 在所述侧壁芯的侧壁上形成侧壁间隔物; 并且通过蚀刻待蚀刻的构件来使用侧壁间隔物和第一硬掩模去除。

公开(公告)号：US07745868B2

公开(公告)日：2010-06-29

申请号：US11984470

申请日：2007-11-19

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L21/7687 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10855

摘要： A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

摘要翻译： 半导体器件可以包括在半导体衬底中具有源极和漏极区域的MOS晶体管，具有到达MOS晶体管上方的源极和漏极区域的第一接触孔的第一层间绝缘体。 第一接触孔中的电池接触插塞与源极和漏极区域接触。 第一层间绝缘体和电池接触插塞之间的第二层间绝缘体具有到达电池接触插塞的第二接触孔。 每个接触塞具有第一和第二部分。 第一部分在第二接触孔中。 第二部分在第一第二层间绝缘体上延伸。 金属阻挡层覆盖接触塞的第二部分的上表面。 电容器各自具有底部电极层，电容绝缘层和顶部电极层。 底部电极层各自具有与金属阻挡层接触的接触部分。

公开(公告)号：US08003465B2

公开(公告)日：2011-08-23

申请号：US12902812

申请日：2010-10-12

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L21/336

CPC分类号： H01L21/32137 ,  H01L21/823885 ,  H01L29/66666

摘要： A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching.

摘要翻译： 半导体器件制造方法可以包括以下处理。 使用具有第一和第二部分作为掩模的第一绝缘膜部分地去除半导体衬底，以形成半导体衬底的第一和第二柱。 在第一和第二支柱的侧表面上形成第二绝缘膜。 在第一和第二绝缘膜上形成硅膜。 去除第一和第二部分的上表面上的硅膜的第一部分。 覆盖半导体衬底上的第一和第二部分的上表面的涂膜。 部分去除涂膜以暴露第一绝缘膜和第二部分硅膜。 第二部分在第一和第二部分的侧表面上。 第二部分通过干蚀刻去除。

公开(公告)号：US20080121960A1

公开(公告)日：2008-05-29

申请号：US11984470

申请日：2007-11-19

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L21/7687 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10855

摘要： A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

摘要翻译： 半导体器件可以包括在半导体衬底中具有源极和漏极区域的MOS晶体管，具有到达MOS晶体管上方的源极和漏极区域的第一接触孔的第一层间绝缘体。 第一接触孔中的电池接触插塞与源极和漏极区域接触。 第一层间绝缘体和电池接触插塞之间的第二层间绝缘体具有到达电池接触插塞的第二接触孔。 每个接触塞具有第一和第二部分。 第一部分在第二接触孔中。 第二部分在第一第二层间绝缘体上延伸。 金属阻挡层覆盖接触塞的第二部分的上表面。 电容器各自具有底部电极层，电容绝缘层和顶部电极层。 底部电极层各自具有与金属阻挡层接触的接触部分。

公开(公告)号：US20060234511A1

公开(公告)日：2006-10-19

申请号：US11404928

申请日：2006-04-17

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L21/311

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L27/10852 ,  H01L28/91

摘要： A method for forming a cylindrical capacitor having a metal-nitride bottom electrode, capacitor insulation film and a top electrode in a DRAM device includes the step of forming a photoresist film on the bottom electrode in a cylindrical hole, removing the photoresist film by using a plasma ashing treatment using non-oxygen gas, and consecutively forming the insulation film and the top electrode on the bottom electrode. The plasma ashing treatment uses a bias power for accelerating the plasma gas into the cylindrical trench.

摘要翻译： 一种在DRAM器件中形成具有金属氮化物底部电极，电容器绝缘膜和顶部电极的圆柱形电容器的方法包括在圆柱形孔中的底部电极上形成光致抗蚀剂膜的步骤，通过使用 使用非氧气的等离子体灰化处理，并且在底部电极上连续地形成绝缘膜和顶部电极。 等离子体灰化处理使用偏置功率来将等离子体气体加速到圆柱形沟槽中。

公开(公告)号：US20060113582A1

公开(公告)日：2006-06-01

申请号：US11289336

申请日：2005-11-30

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer. The blockage of a cylinder is prevented by etching the upper low-concentration impurity sublayer in a lower region of the cylinder and thereby reducing the crystal grain size of hemispherical silicon grains formed in the lower region.

摘要翻译： 根据本发明的半导体器件包括圆柱形电容器。 用作圆筒形电容器的下电极的非晶硅层具有包括下部高浓度杂质子层和上部低浓度杂质子层的两层结构。 通过在圆柱体的下部区域中蚀刻上部低浓度杂质子层，从而降低在下部区域形成的半球形硅粒子的晶粒尺寸，可以防止气缸堵塞。

公开(公告)号：US07772065B2

公开(公告)日：2010-08-10

申请号：US12024068

申请日：2008-01-31

申请人： Masahiko Ohuchi

发明人： Masahiko Ohuchi

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10855 ,  Y10S257/906 ,  Y10S257/908

摘要： A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.

摘要翻译： 半导体存储器件包括形成在有源区中的扩散区域; 分别连接到扩散区的电池触点; 支柱分别连接到电池触点; 连接到支柱的位线; 电容器触点分别连接到支柱; 和分别连接到电容器触点的存储电容器。 因此，电池触点和电容器触点之间存在支柱，因此使电容器触点的深度相应地更短。 因此，可以防止短路缺陷的发生，同时降低电容器触点的电阻值。