公开(公告)号：US09379201B2

公开(公告)日：2016-06-28

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L21/4763 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L21/768 ,  H01L29/872 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/304 ,  H01L23/48 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US09973431B2

公开(公告)日：2018-05-15

申请号：US14966844

申请日：2015-12-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Mishra ,  Christopher Kong Yee Chun ,  Chiew-Guan Tan ,  Gordon Lee ,  Todd Sutton

IPC: H04L1/00 ,  H04L12/801 ,  H04L5/14 ,  H04L12/933 ,  H04W28/02 ,  H04W52/02

CPC classification number: H04L47/12 ,  G06F13/4278 ,  G06F13/4295 ,  H04L5/14 ,  H04L49/109 ,  H04W28/0221 ,  H04W52/0229 ,  Y02D70/122 ,  Y02D70/26

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

公开(公告)号：US09614529B1

公开(公告)日：2017-04-04

申请号：US15012696

申请日：2016-02-01

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/00 ,  H03K19/0185

CPC classification number: H03K19/018507 ,  H03K19/0016 ,  H03K19/018514

Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

公开(公告)号：US20150303906A1

公开(公告)日：2015-10-22

申请号：US14254706

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：US08754677B2

公开(公告)日：2014-06-17

申请号：US13683053

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/00

CPC classification number: G05F1/565

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract translation: 公开了一种输入/输出（I / O）驱动器，其采用补偿电路来限制驱动器的器件之间的电压超过限定的阈值，以允许较低电压的器件实现驱动器的操作。 特别地，驱动器采用包括耦合在第一电压轨和驱动器的输出之间的第一和第二开关器件的上拉电路。 驱动器采用包括耦合在输出端和第二电压轨道之间的第三和第四开关器件的下拉电路。 I / O驱动器采用补偿电路，其被配置为在适当的时间向第一和第二开关器件之间的节点和第三和第四开关器件之间的节点施加补偿电压，以保持跨越第二和第三开关器件的相应电压 在驾驶员的操作期间，切换设备处于或低于定义的阈值，例如可靠性限制。

公开(公告)号：US11251794B2

公开(公告)日：2022-02-15

申请号：US17008068

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Sumit Rao ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

公开(公告)号：US11171649B1

公开(公告)日：2021-11-09

申请号：US17071796

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Aliasgar Presswala ,  Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K3/356

Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

公开(公告)号：US10892760B1

公开(公告)日：2021-01-12

申请号：US16653391

申请日：2019-10-15

Applicant: QUALCOMM Incorporated

Inventor： Sumit Rao ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

公开(公告)号：US20190317579A1

公开(公告)日：2019-10-17

申请号：US15952071

申请日：2018-04-12

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Chiew-Guan Tan ,  Alex Kuang-Hsuan Tu

IPC: G06F1/26

Abstract: Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

公开(公告)号：US20180287609A1

公开(公告)日：2018-10-04

申请号：US15478063

申请日：2017-04-03

Applicant: QUALCOMM Incorporated

Inventor： Yeshwanth Kumar Mallavajula ,  Wilson Chen ,  Chiew-Guan Tan

IPC: H03K19/00 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K3/356017 ,  H03K3/356034 ,  H03K3/35613 ,  H03K17/063 ,  H03K17/6872 ,  H03K19/018521 ,  H03K19/018528

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.