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    Self-biased charge pump
    2.
    发明授权
    Self-biased charge pump 有权
    自偏置电荷泵

    公开(公告)号：US09473022B2

    公开(公告)日：2016-10-18

    申请号：US14618369

    申请日：2015-02-10

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Lai Kan Leung ,  Jong Min Park

    IPC: H03L7/06 ,  H02M3/07 ,  H03L7/08

    CPC classification number: H02M3/07 ,  H03L7/08 ,  H03L7/0895

    Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

    Abstract translation: 一种装置，包括：被配置为产生电流的电流源; 耦合到电流源的开关电流源电路和第一偏置节点，以允许电流流过开关电流源电路进入第一偏置节点; 第一偏置电路，被配置为从相位检测器接收第一控制信号，所述第一偏置电路被配置为响应于所述第一控制信号镜像流过所述开关电流源电路的电流; 第二偏置电路，耦合到输出节点处的第一偏置电路和第二偏置节点，第二偏置电路被配置为从相位检测器接收第二控制信号; 以及跨导放大器，被配置为从所述输出节点接收反馈信号并产生输出电流以控制所述第二偏置节点。

    Phase interpolation-based fractional-N sampling phase-locked loop
    3.
    发明授权
    Phase interpolation-based fractional-N sampling phase-locked loop 有权

    公开(公告)号：US11411567B2

    公开(公告)日：2022-08-09

    申请号：US17117240

    申请日：2020-12-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： Masoud Moslehi Bajestan ,  Giovanni Marucci ,  Dongmin Park ,  Marco Zanuso ,  Yiwu Tang

    IPC: H03L7/099 ,  H03J7/04 ,  H03L7/02 ,  H03L7/093 ,  H03M3/00 ,  H03K3/037

    Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

    Sampling phase-locked loop (PLL)
    5.
    发明授权
    Sampling phase-locked loop (PLL) 有权

    公开(公告)号：US09991897B1

    公开(公告)日：2018-06-05

    申请号：US15415201

    申请日：2017-01-25

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Jong Min Park ,  Yiwu Tang

    IPC: H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H04L7/033

    CPC classification number: H03L7/091 ,  H03L7/085 ,  H03L7/099 ,  H04L7/0331

    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.

    Self-biased charge pump
    7.
    发明授权
    Self-biased charge pump 有权

    公开(公告)号：US09397558B1

    公开(公告)日：2016-07-19

    申请号：US14618369

    申请日：2015-02-10

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Lai Kan Leung ,  Jong Min Park

    IPC: H03L7/06 ,  H02M3/07 ,  H03L7/08

    Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

    Current-mode buffer with output swing detector for high frequency clock interconnect
    8.
    发明授权
    Current-mode buffer with output swing detector for high frequency clock interconnect 有权
    具有输出摆幅检测器的电流模式缓冲器，用于高频时钟互连

    公开(公告)号：US08766674B1

    公开(公告)日：2014-07-01

    申请号：US13834861

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Li Liu ,  Sujiang Rong

    IPC: H03K3/00 ,  H03K7/02 ,  H03K5/02 ,  H03K17/16

    CPC classification number: H03K5/08 ,  H03K6/02

    Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

    Abstract translation: 高速电流模式时钟驱动器包括反馈电路，以将偏置节点的电压摆幅保持在限定的范围内。 电流模式时钟驱动器包括在其栅极端子处接收振荡信号的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的漏极端子分别耦合到输出端耦合到公共节点的第一和第二可变电导率电路的输入端。 控制电路响应于公共节点的电压摆幅的减小而增加第一和第二可变电导率电路的电导率，并且响应于公共节点的电压摆幅的增加而降低第一和第二可变电导率电路的电导率。 第一和第二可变电导率电路分别是PMOS和NMOS晶体管。

    PROGRAMMABLE CLOCK DIVIDER FOR RADIO FREQUENCY (RF) MIXERS
    9.
    发明申请
    PROGRAMMABLE CLOCK DIVIDER FOR RADIO FREQUENCY (RF) MIXERS 有权

    公开(公告)号：US20240413962A1

    公开(公告)日：2024-12-12

    申请号：US18333217

    申请日：2023-06-12

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Dongling Pan ,  Yiwu Tang

    IPC: H04L7/00 ,  H03K3/037 ,  H03K21/02

    Abstract: This disclosure provides systems, methods, and devices for wireless communications that support configurable clock dividers for mixer operation in a radio frequency front end (RFFE). In a first aspect, an apparatus for wireless communications includes a first clock loop comprising a first plurality of latches generating a first plurality of clock signals with a corresponding first plurality of phases; and a second clock loop comprising a second plurality of latches generating a second plurality of clock signals with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal. Other aspects and features are also claimed and described.

    Prescaler for a frequency divider
    10.
    发明授权
    Prescaler for a frequency divider 有权

    公开(公告)号：US11349483B1

    公开(公告)日：2022-05-31

    申请号：US17391406

    申请日：2021-08-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： Shilei Hao ,  Yunliang Zhu ,  Yiwu Tang ,  Dongmin Park

    IPC: H03K23/00 ,  H03K23/44 ,  H03K3/356 ,  H03K21/10 ,  H03K23/40

    Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

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