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公开(公告)号：US09654002B2
公开(公告)日：2017-05-16
申请号：US14918893
申请日：2015-10-21
Applicant: QUALCOMM Incorporated
Inventor： James Thomas Doyle , Farsheed Mahmoudi , Chuang Zhang , Zhengming Fu , Sassan Shahrokhinia
CPC classification number: H02M3/158 , H02M1/38 , H02M3/157 , H02M2001/0012 , H02M2001/0048 , Y02B70/1491
Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.
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公开(公告)号：US09641073B2
公开(公告)日：2017-05-02
申请号：US14845809
申请日：2015-09-04
Applicant: QUALCOMM Incorporated
Inventor： Farsheed Mahmoudi , James Thomas Doyle , Amirali Shayan
CPC classification number: H02M3/157 , H02M1/36 , H02M3/156 , H02M3/33507 , H02M2001/0003 , H02M2001/0025 , H02M2001/0035 , Y02B70/16
Abstract: A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.
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公开(公告)号：US10199152B2
公开(公告)日：2019-02-05
申请号：US14743623
申请日：2015-06-18
Applicant: QUALCOMM Incorporated
Inventor： Mete Erturk , Ravindra Vaman Shenoy , Kwan-yu Lai , Jitae Kim , Donald William Kidwell, Jr. , Jon Bradley Lasiter , James Thomas Doyle , Omar James Bchir
IPC: H01F5/00 , H01F27/28 , H01F1/147 , H01F27/24 , H01F41/02 , H01F41/14 , H05K1/11 , H05K1/18 , H01F17/00 , H01F41/04 , H05K1/16 , H01L23/64 , H01L23/00
Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.
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公开(公告)号：US09891646B2
公开(公告)日：2018-02-13
申请号：US14606753
申请日：2015-01-27
Applicant: QUALCOMM Incorporated
Inventor： Zhengming Fu , James Thomas Doyle , Nazanin Darbanian , Shree Krishna Pandey , Yi Cao
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
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公开(公告)号：US09785222B2
公开(公告)日：2017-10-10
申请号：US14579899
申请日：2014-12-22
Applicant: QUALCOMM Incorporated
Inventor： James Thomas Doyle , Zhengming Fu , Farsheed Mahmoudi , Amirali Shayan Arani , Nazanin Darbanian
CPC classification number: G06F1/3287 , G05F1/575 , G06F1/3296 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
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Patent Agency Ranking
6.发明申请Start Up Method for Switching Converters using the same Reference Voltage in the Error Amplifier and PWM Comparator 有权在误差放大器和PWM比较器中使用相同的参考电压开关转换器的启动方法公开(公告)号：US20170070141A1
公开(公告)日：2017-03-09
申请号：US14845809
申请日：2015-09-04
Applicant: QUALCOMM Incorporated
Inventor： Farsheed Mahmoudi , James Thomas Doyle , Amirali Shayan
IPC: H02M3/157
CPC classification number: H02M3/157 , H02M1/36 , H02M3/156 , H02M3/33507 , H02M2001/0003 , H02M2001/0025 , H02M2001/0035 , Y02B70/16
Abstract: A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.
Abstract translation: 提供了一种开关电源，其包括用于产生用于控制开关模式电源中的电源开关的脉宽调制（PWM）控制器时钟信号的比较器。 开关模式电源被配置为叠加具有误差电压的无DC版本的斜坡电压以产生组合电压。 比较器将组合电压与参考电压进行比较，以产生PWM控制器时钟信号。
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7.发明申请CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER 有权在同步转换器上提供死区时间调整的电路和方法公开(公告)号：US20160118893A1
公开(公告)日：2016-04-28
申请号：US14918893
申请日：2015-10-21
Applicant: QUALCOMM Incorporated
Inventor： James Thomas Doyle , Farsheed Mahmoudi , Chuang Zhang , Zhengming Fu , Sassan Shahrokhinia
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M1/38 , H02M3/157 , H02M2001/0012 , H02M2001/0048 , Y02B70/1491
Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.
Abstract translation: 公开了一种用于在诸如同步降压转换器的电压调节器处有效地使用电力的装置和方法。 同步降压转换器包括分别由第一控制信号和第二控制信号操作的第一开关和第二开关，其中第一和第二控制信号具有相应的相位差。 逻辑电路针对第一控制信号和第二控制信号之间的相位差的迭代变化来测量输入脉宽调制（PWM）信号的占空比。 逻辑电路选择与PWM信号的最小值相对应的相位差，从而优化同步降压转换器的死区时间。 逻辑电路可以包括数字脉宽调制器。
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公开(公告)号：US10470309B2
公开(公告)日：2019-11-05
申请号：US14859320
申请日：2015-09-20
Applicant: QUALCOMM Incorporated
Inventor： Mete Erturk , Farsheed Mahmoudi , James Thomas Doyle , Ravindra Vaman Shenoy , Jitae Kim
IPC: H05K1/16 , H01L27/01 , H01L23/522 , H01L49/02 , H01L23/498 , H05K1/11 , H05K3/42
Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.
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9.发明申请Circuits and Methods Providing Three-Level Signals At A Synchronous Buck Converter 有权在同步降压转换器中提供三电平信号的电路和方法公开(公告)号：US20160380543A1
公开(公告)日：2016-12-29
申请号：US15248267
申请日：2016-08-26
Applicant: QUALCOMM Incorporated
Inventor： Chuang Zhang , James Thomas Doyle , Farsheed Mahmoudi , Amirali Shayan Arani
CPC classification number: H02M3/158 , H02M1/14 , H02M7/483 , H02M2003/072
Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.
Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器进行充电和放电 电容器 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。
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10.发明申请CIRCUITS AND METHODS PROVIDING THREE-LEVEL SIGNALS AT A SYNCHRONOUS BUCK CONVERTER 有权在同步转换器上提供三级信号的电路和方法公开(公告)号：US20160118886A1
公开(公告)日：2016-04-28
申请号：US14630318
申请日：2015-02-24
Applicant: QUALCOMM Incorporated
Inventor： Chuang Zhang , James Thomas Doyle , Farsheed Mahmoudi , Amirali Shayan Arani
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M1/14 , H02M7/483 , H02M2003/072
Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.
Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器进行充电和放电 电容器 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。
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