中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.011 seconds)

    DELAY ELEMENT GAIN CALIBRATION
    1.
    发明申请
    DELAY ELEMENT GAIN CALIBRATION 有权

    公开(公告)号：US20250141455A1

    公开(公告)日：2025-05-01

    申请号：US18497464

    申请日：2023-10-30

    Applicant: QUALCOMM Incorporated

    Inventor： Yunliang ZHU ,  Yiwu TANG

    IPC: H03L7/081 ,  H03K5/00 ,  H03K5/131 ,  H03L7/085

    Abstract: Certain aspects of the present disclosure are directed towards a method for delay element calibration. The method generally includes: incrementing a calibration delay control signal provided to a delay element to generate an output clock signal by delaying an input clock signal; comparing, via a phase detector (PD), the input clock signal and the output clock signal to generate a PD output signal; and accumulating, via a first accumulator, the PD output signal to generate a calibration output signal.

    LOCKING MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS WITH A SINGLE PHASE-LOCKED LOOP
    2.
    发明申请
    LOCKING MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS WITH A SINGLE PHASE-LOCKED LOOP 有权
    带有单相锁定环路的锁定多电压控制振荡器

    公开(公告)号：US20150295583A1

    公开(公告)日：2015-10-15

    申请号：US14251331

    申请日：2014-04-11

    Applicant: Qualcomm Incorporated

    Inventor： Yiwu TANG ,  Jong Min PARK ,  Serkan SAYILIR ,  Chiewcharn NARATHONG

    IPC: H03L7/099 ,  H03L7/081

    CPC classification number: H03L7/099 ,  H03L7/081 ,  H03L7/093

    Abstract: Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.

    Abstract translation: 锁定多个VCO以产生多个LO频率，包括：从多个VCO接收多个分割的VCO反馈信号; 接收乘以所述多个VCO的预定数量的参考信号; 在包括数字环路滤波器的单个PLL电路中产生和处理倍增参考信号与多个分压VCO反馈信号之间的预定数量的相位差，以接收和处理相位差并产生（产生）滤波器输出，其中， 数字环路滤波器包括等于预定数量的多个延迟单元; 以及基于滤波器输出产生并输出（延迟的）多个VCO的控制电压。

    MULTIPHASE OSCILLATING SIGNAL GENERATION AND ACCURATE FAST FREQUENCY ESTIMATION
    4.
    发明申请
    MULTIPHASE OSCILLATING SIGNAL GENERATION AND ACCURATE FAST FREQUENCY ESTIMATION 审中-公开
    多相振荡信号的生成和精确的快速估计

    公开(公告)号：US20160065195A1

    公开(公告)日：2016-03-03

    申请号：US14471530

    申请日：2014-08-28

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad FARAZIAN ,  Serkan SAYILIR ,  Marco ZANUSO ,  Yiwu TANG

    IPC: H03K5/15 ,  H03H11/22 ,  H03H11/20

    CPC classification number: H03K5/1506 ,  H03H11/22 ,  H03H19/002 ,  H03K2005/00286

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating multiple oscillating signals having different phases. One example multiphase generating circuit generally includes a first phase shifting circuit configured to phase shift an input signal having an input frequency, such that an output signal of the first phase shifting circuit has a first phase difference with respect to the input signal; a first frequency dividing circuit configured to receive the input signal and output a first set of signals having a first frequency less than the input frequency of the input signal; and a second frequency dividing circuit configured to receive the output signal of the first phase shifting circuit and output a second set of signals having a second frequency less than the input frequency of the input signal. The multiphase signals may be used for fast frequency estimation of the input signal or in N-path filters.

    Abstract translation: 本公开的某些方面提供了用于产生具有不同相位的多个振荡信号的方法和装置。 一个示例性多相生成电路通常包括：第一移相电路，被配置为使具有输入频率的输入信号相移，使得第一移相电路的输出信号相对于输入信号具有第一相位差; 第一分频电路，被配置为接收所述输入信号并输出​​具有小于所述输入信号的输入频率的第一频率的第一组信号; 以及第二分频电路，被配置为接收第一移相电路的输出信号并输出​​具有小于输入信号的输入频率的第二频率的第二组信号。 多相信号可用于输入信号的快速频率估计或N路径滤波器。

    PHASE INTERPOLATION-BASED FRACTIONAL-N SAMPLING PHASE-LOCKED LOOP
    6.
    发明申请
    PHASE INTERPOLATION-BASED FRACTIONAL-N SAMPLING PHASE-LOCKED LOOP 有权

    公开(公告)号：US20220190833A1

    公开(公告)日：2022-06-16

    申请号：US17117240

    申请日：2020-12-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： Masoud MOSLEHI BAJESTAN ,  Giovanni MARUCCI ,  Dongmin PARK ,  Marco ZANUSO ,  Yiwu TANG

    IPC: H03L7/093 ,  H03K3/037 ,  H03M3/00

    Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

    P-TYPE METAL-OXIDE-SEMICONDUCTOR (PMOS) LOW DROP-OUT (LDO) REGULATOR
    7.
    发明申请
    P-TYPE METAL-OXIDE-SEMICONDUCTOR (PMOS) LOW DROP-OUT (LDO) REGULATOR 有权

    公开(公告)号：US20210072778A1

    公开(公告)日：2021-03-11

    申请号：US16561839

    申请日：2019-09-05

    Applicant: QUALCOMM Incorporated

    Inventor： Yue CHAO ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN ,  Yiwu TANG

    IPC: G05F1/575 ,  G05F1/595 ,  H03F3/45

    Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

    MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER
    8.
    发明申请
    MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER 有权
    多方位接收器与多个合成器在载波聚合收发器

    公开(公告)号：US20150333815A1

    公开(公告)日：2015-11-19

    申请号：US14677056

    申请日：2015-04-02

    Applicant: QUALCOMM Incorporated

    Inventor： Lai Kan LEUNG ,  Chiewcharn NARATHONG ,  Rajagopalan RANGARAJAN ,  Dongling PAN ,  Yiwu TANG ,  Aleksandar Miodrag TASIC

    IPC: H04B7/08 ,  H04L27/152 ,  H04B1/16

    CPC classification number: H04B7/0897 ,  H04B1/0082 ,  H04B1/16 ,  H04L27/152

    Abstract: Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency.

    Abstract translation: 本公开的某些方面提供具有多个合成器的多路分集接收机。 这种多路分集接收机可以在载波聚合（CA）收发机中实现。 一个示例性的无线接收分集电路通常包括用于处理接收信号的三个或更多个接收路径和被配置为产生本地振荡信号以下变频接收信号的两个或多个频率合成电路。 每个频率合成电路由至多两个接收路径共享，并且每对频率合成电路可以产生具有相同频率的一对本地振荡信号。

    LOW POWER DIGITAL-TO-TIME CONVERTER (DTC) LINEARIZATION
    9.
    发明申请
    LOW POWER DIGITAL-TO-TIME CONVERTER (DTC) LINEARIZATION 有权

    公开(公告)号：US20220393565A1

    公开(公告)日：2022-12-08

    申请号：US17340953

    申请日：2021-06-07

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Siu-Chi LI ,  Tomas O'SULLIVAN ,  Jianjun YU ,  Yiwu TANG

    IPC: H02M1/00 ,  H02M1/084

    Abstract: An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

Patent Agency Ranking