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    Fractional phase locked loop (PLL) architecture
    6.
    发明授权
    Fractional phase locked loop (PLL) architecture 有权
    分数锁相环（PLL）架构

    公开(公告)号：US09577646B1

    公开(公告)日：2017-02-21

    申请号：US14820894

    申请日：2015-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Hanan Cohen ,  Eskinder Hailu ,  Kenneth Luis Arcudia

    IPC: H03K21/10

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

    Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range
    8.
    发明授权
    Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range 有权

    公开(公告)号：US10355701B2

    公开(公告)日：2019-07-16

    申请号：US15675160

    申请日：2017-08-11

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Eskinder Hailu ,  Zhuo Gao

    IPC: H03L7/089 ,  H03L7/087 ,  H03L7/099 ,  H03L7/095 ,  H03B5/12 ,  G06F1/10 ,  H03K3/03

    Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

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