公开(公告)号：US20240321861A1

公开(公告)日：2024-09-26

申请号：US18189482

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Hyunwoo Park ,  Ming-Huei Lin ,  Junjing Bao

IPC: H01L27/02 ,  H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A logic circuit includes a first circuit having a first diffusion region and a second diffusion region and a second circuit having a third diffusion region, and a fourth diffusion region. First devices in the first circuit each include a portion of the first diffusion region and a portion of the second diffusion region. Second devices in the second circuit each include portions of the third and fourth diffusion regions. The first diffusion region is between the second diffusion region and the third diffusion region. The third diffusion region is between the first diffusion region and the fourth diffusion region. A second distance from a first side of the fourth diffusion region to a second side of the third diffusion region is less than a first distance from a first side of the first diffusion region to a second side of the second diffusion region.

公开(公告)号：US12051534B2

公开(公告)日：2024-07-30

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01F27/29 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02

CPC classification number: H01F27/29 ,  H01F17/0013 ,  H01F41/041 ,  H01L28/10 ,  H01F2017/0073

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20240234418A9

公开(公告)日：2024-07-11

申请号：US18047954

申请日：2022-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US20240136357A1

公开(公告)日：2024-04-25

申请号：US18047954

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US11744059B2

公开(公告)日：2023-08-29

申请号：US16712063

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H10B10/00 ,  H01L29/66 ,  G11C11/412 ,  H01L29/78 ,  H01L27/02

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L27/0207 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

公开(公告)号：US11295991B2

公开(公告)日：2022-04-05

申请号：US16798947

申请日：2020-02-24

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/02 ,  H01L27/092

Abstract: To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.

公开(公告)号：US11222952B2

公开(公告)日：2022-01-11

申请号：US16749897

申请日：2020-01-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/201 ,  H01L29/66 ,  H01L29/78 ,  H01L29/43

Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

公开(公告)号：US11145649B2

公开(公告)日：2021-10-12

申请号：US16408207

申请日：2019-05-09

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao

IPC: H01L27/088 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78

Abstract: A semiconductor device with low parasitic capacitance comprises a substrate. The semiconductor device also comprises a gate region on the substrate. The semiconductor device further comprises a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.

公开(公告)号：US10892322B2

公开(公告)日：2021-01-12

申请号：US16138170

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Jie Deng

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/8234 ,  H01L27/118 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

公开(公告)号：US10833017B2

公开(公告)日：2020-11-10

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Youseok Suh ,  Jihong Choi ,  Junjing Bao

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.