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    Power multiplexing with flip-flops
    2.
    发明授权
    Power multiplexing with flip-flops 有权

    公开(公告)号：US09673787B2

    公开(公告)日：2017-06-06

    申请号：US14861503

    申请日：2015-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Jeffrey Gemar ,  Ramaprasath Vilangudipitchai

    IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

    Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

    Integrated circuit power rail multiplexing
    3.
    发明授权
    Integrated circuit power rail multiplexing 有权

    公开(公告)号：US09654101B2

    公开(公告)日：2017-05-16

    申请号：US14814409

    申请日：2015-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

    IPC: H03K17/693 ,  H03K19/00

    CPC classification number: H03K17/693 ,  H03K19/0016

    Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

    ADAPTIVE POWER MULTIPLEXING WITH A POWER DISTRIBUTION NETWORK
    5.
    发明申请
    ADAPTIVE POWER MULTIPLEXING WITH A POWER DISTRIBUTION NETWORK 有权

    公开(公告)号：US20180004276A1

    公开(公告)日：2018-01-04

    申请号：US15199567

    申请日：2016-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Mong Chit Wong ,  Nam Dang ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Yu Huang ,  Lipeng Cao

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/263 ,  H01L23/50 ,  H02J1/08 ,  H02J1/108 ,  H02J9/061

    Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

    INTEGRATED CIRCUIT POWER RAIL MULTIPLEXING
    6.
    发明申请
    INTEGRATED CIRCUIT POWER RAIL MULTIPLEXING 有权
    集成电路功率轨道多路复用

    公开(公告)号：US20170033796A1

    公开(公告)日：2017-02-02

    申请号：US14814409

    申请日：2015-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

    IPC: H03K17/693

    CPC classification number: H03K17/693 ,  H03K19/0016

    Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

    Abstract translation: 本文公开了一种用于通过电力轨道复用进行电力管理的集成电路（IC）。 在示例方面，IC包括第一电力轨，第二电力轨和负载电力轨。 IC还包括第一组晶体管，其包括耦合到第一电力轨的第一晶体管和包括耦合到第二电力轨的第二晶体管的第二组晶体管。 IC还包括电力多路复用器电路，其被配置为通过顺序地关闭第一组晶体管的第一晶体管，然后顺序地接通第一组晶体管的第一晶体管，从而将负载电源轨从第一电力轨到第二电力轨的电​​力切换 第二组晶体管的第二晶体管。

    Adjustable power rail multiplexing
    7.
    发明授权
    Adjustable power rail multiplexing 有权

    公开(公告)号：US09852859B2

    公开(公告)日：2017-12-26

    申请号：US14981183

    申请日：2015-12-28

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

    IPC: H01H47/00 ,  H03K19/00

    CPC classification number: H01H47/00 ,  H03K19/0008

    Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

    ADJUSTABLE POWER RAIL MULTIPLEXING
    8.
    发明申请
    ADJUSTABLE POWER RAIL MULTIPLEXING 有权

    公开(公告)号：US20170186576A1

    公开(公告)日：2017-06-29

    申请号：US14981183

    申请日：2015-12-28

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

    IPC: H01H47/00

    CPC classification number: H01H47/00 ,  H03K19/0008

    Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

    POWER MULTIPLEXER FOR INTEGRATED CIRCUIT POWER GRID EFFICIENCY
    9.
    发明申请
    POWER MULTIPLEXER FOR INTEGRATED CIRCUIT POWER GRID EFFICIENCY 有权
    集成电路功率多路复用器功率因数

    公开(公告)号：US20170060224A1

    公开(公告)日：2017-03-02

    申请号：US14836694

    申请日：2015-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Tauseef Kazi ,  Alain Dominique Artieri

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203

    Abstract: An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

    Abstract translation: 集成电路设置有低功率岛，其包括嵌入式存储器电力域，其可以选择性地耦合到在第一电力轨上提供的有源模式电源电压或提供在第二电力轨上的睡眠模式电源电压 。

    Power management with flip-flops
    10.
    发明授权
    Power management with flip-flops 有权
    电源管理与触发器

    公开(公告)号：US09473113B1

    公开(公告)日：2016-10-18

    申请号：US14864101

    申请日：2015-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan ,  Lipeng Cao ,  Sai Pradeep Kochuri ,  Parissa Najdesamii

    IPC: H03K3/02 ,  H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

    Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

    Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电源轨，可折叠电源轨，多个触发器和电源管理电路。 多个触发器的每个触发器包括耦合到可折叠电源轨的主部和耦合到恒功率轨的从部。 功率管理电路被配置为将时钟信号和保持信号组合成组合的控制信号，并将组合的控制信号提供给多个触发器的每个触发器。

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