公开(公告)号：US09800271B2

公开(公告)日：2017-10-24

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US09281039B2

公开(公告)日：2016-03-08

申请号：US13953771

申请日：2013-07-30

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/15 ,  G11C11/16 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。

公开(公告)号：US09406354B1

公开(公告)日：2016-08-02

申请号：US14693755

申请日：2015-04-22

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26

Abstract: A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.

Abstract translation: 用于存储单元的读取电路可以包括用于感测电流变化的集成逻辑电路。 集成逻辑感测电路可以是偏移消除单端集成逻辑感测电路。 电路可以包括耦合到电源电压的偏移消除单端感测电路，具有耦合到偏移消除单端感测电路的读出放大器输入和读出放大器输出的偏移消除单端读出放大器电路，以及耦合到 到感测电路输出和地。

公开(公告)号：US20150036409A1

公开(公告)日：2015-02-05

申请号：US13953771

申请日：2013-07-30

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/16 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。

公开(公告)号：US09378781B1

公开(公告)日：2016-06-28

申请号：US14683008

申请日：2015-04-09

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation; Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C16/28 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C5/10 ,  H03F3/16

CPC classification number: G11C7/08 ,  G11C5/10 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/28 ,  G11C2013/0042 ,  G11C2013/0054 ,  H03F3/45179 ,  H03F3/45775 ,  H03F2203/45212

Abstract: An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage operation. For example, a sense amplifier may include a second pair of sensing switches cross coupled in parallel with a first pair of sensing switches and a pair of degeneration transistors coupled in line before a pair of load transistors.

Abstract translation: 根据本公开的一些示例的偏移消除读出放大器可以使用双重感测余量结构和正反馈来实现更好的性能特征和读取稳定性而不需要多级操作。 例如，读出放大器可以包括与第一对感测开关并联耦合的第二对感测开关和一对在一对负载晶体管之前串联耦合的退化晶体管。

公开(公告)号：US09111623B1

公开(公告)日：2015-08-18

申请号：US14179115

申请日：2014-02-12

Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Ji-su Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054

Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.

Abstract translation: 电阻式存储器感测方法包括通过NMOS偏移消除电流锁存读出放大器电路（NOC-CLSA）来感测偏移消除双级感测电路（OCDS-SC）的输出。 NOC-CLSA配置有降低的输入电容和降低的失调电压。 NOC-CLSA的输入晶体管耦合在锁存电路和地之间。 在NOC-CLSA操作的预充电步骤期间，OCDS-SC的第一相输出由NOC-CLSA存储。 在NOC-CLSA操作的偏移消除步骤期间，OCDS-SC的第二相输出由NOC-CLSA存储。 通过流水线OCDS-SC和NOC-CLSA，克服了OCDS-SC的感测延迟损失。

公开(公告)号：US20140269031A1

公开(公告)日：2014-09-18

申请号：US13835251

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。

公开(公告)号：US10263645B2

公开(公告)日：2019-04-16

申请号：US15716451

申请日：2017-09-26

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

公开(公告)号：US09666259B1

公开(公告)日：2017-05-30

申请号：US15097166

申请日：2016-04-12

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Byung Kyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C11/1675

Abstract: A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.

公开(公告)号：US09502088B2

公开(公告)日：2016-11-22

申请号：US14499155

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Jisu Kim ,  Taehui Na ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract translation: 系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。 负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。 基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。 产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。 存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。