公开(公告)号：US12181963B2

公开(公告)日：2024-12-31

申请号：US17485092

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Yi-Hung Tseng ,  Marzio Pedrali-Noy ,  Charles James Persico ,  Mustafa Keskin

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/40 ,  H03K3/037 ,  H03L7/08

Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.

公开(公告)号：US20230098996A1

公开(公告)日：2023-03-30

申请号：US17485092

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Yi-Hung Tseng ,  Marzio Pedrali-Noy ,  Charles James Persico ,  Mustafa Keskin

IPC: G06F11/07 ,  G06F13/40

Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.

公开(公告)号：US09866234B1

公开(公告)日：2018-01-09

申请号：US15589684

申请日：2017-05-08

Applicant: QUALCOMM Incorporated

Inventor： Yi-Hung Tseng

IPC: H03M1/66 ,  H03M1/06 ,  G06F1/10 ,  H03M1/74 ,  H03K5/24 ,  H03M1/00 ,  H03K19/003

CPC classification number: H03M1/0678 ,  G06F1/10 ,  H03K5/2481 ,  H03K19/00315 ,  H03K19/00361 ,  H03M1/00 ,  H03M1/742 ,  H03M1/745 ,  H03M1/747

Abstract: Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.

公开(公告)号：US20150364170A1

公开(公告)日：2015-12-17

申请号：US14302727

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Philip Michael Clovis ,  Yi-Hung Tseng ,  Xuhao Huang ,  Sushma Chilukuri

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03L7/07 ,  H03L7/0814

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

公开(公告)号：US20240339998A1

公开(公告)日：2024-10-10

申请号：US18745714

申请日：2024-06-17

Applicant: Qualcomm Incorporated

Inventor： Yi-Hung Tseng ,  Marzio Pedrali-Noy ,  Charles James Persico

IPC: H03K17/082 ,  H02H1/00

CPC classification number: H03K17/082 ,  H02H1/0007

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

公开(公告)号：US12040785B2

公开(公告)日：2024-07-16

申请号：US17485005

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Yi-Hung Tseng ,  Marzio Pedrali-Noy ,  Charles James Persico

IPC: H03K17/082 ,  H02H1/00

CPC classification number: H03K17/082 ,  H02H1/0007

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

公开(公告)号：US10979068B1

公开(公告)日：2021-04-13

申请号：US16577074

申请日：2019-09-20

Applicant: QUALCOMM INCORPORATED

Inventor： Yi-Hung Tseng ,  Karthik Nagarajan

IPC: H03M1/66 ,  H04B1/40 ,  H03L7/099 ,  H03L7/093

Abstract: A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.

公开(公告)号：US09478268B2

公开(公告)日：2016-10-25

申请号：US14302727

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Philip Michael Clovis ,  Yi-Hung Tseng ,  Xuhao Huang ,  Sushma Chilukuri

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F13/16 ,  G11C29/02 ,  H03L7/081 ,  H03L7/07

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03L7/07 ,  H03L7/0814

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

公开(公告)号：US09191193B1

公开(公告)日：2015-11-17

申请号：US14335185

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Xuhao Huang ,  Yi-Hung Tseng ,  Philip Michael Clovis ,  Sushma Chilukuri

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/081

CPC classification number: H03L7/10 ,  H03L7/0812 ,  H03L7/0814

Abstract: A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.

Abstract translation: 时钟同步电路包括产生多个延迟时钟的多相时钟发生器，每个延迟时钟具有关于源时钟的唯一延迟。 时钟同步电路还包括选择电路，其根据相位误差选择延迟时钟之一，以形成被驱动到本地时钟路径中并在时钟同步电路处接收的本地时钟作为接收到的本地时钟。 选择电路通过将接收到的本地时钟与参考时钟进行比较来确定相位误差。