公开(公告)号：US09608935B2

公开(公告)日：2017-03-28

申请号：US14479728

申请日：2014-09-08

Applicant: QUALCOMM Technologies Inc.

Inventor： Philippe Martin ,  Philippe Boucard

IPC: H04L12/933 ,  H04L12/805 ,  H04L12/865 ,  H04L12/863 ,  G06F15/78

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L47/365 ,  H04L47/6275 ,  H04L47/628

Abstract: Systems and methods relate to a network on chip (NoC) which includes one or more channels configured to carry data packets in a first direction, the first direction having an upstream end and a downstream end. A tunnel is configured between an upstream element at the upstream end and a downstream element at the downstream end. The tunnel includes common wires which are shared by the one or more channels. The tunnel is configured to transmit data packets of two or more formats on the common wires based on common signals. common signals comprise data signals to transmit one or more of data, control, or debug information belonging to the data packets on the common wires, and framing signals to control transmission of the data signals on the common wires.

公开(公告)号：US09465749B2

公开(公告)日：2016-10-11

申请号：US13969559

申请日：2013-08-17

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/02 ,  G06F12/10 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract translation: 具有预取地址发生器的系统，其耦合到包括翻译高速缓存的系统转换后备缓冲器。 发送预取请求以进行页面地址转换，以便将来预测未来的正常请求。 预取请求被过滤，只能发布用于不太可能在翻译缓存中的地址转换。 待处理的预取请求仅限于可配置或可编程的数字。 这种系统是从硬件描述语言表示模拟的。

公开(公告)号：US09396130B2

公开(公告)日：2016-07-19

申请号：US13969451

申请日：2013-08-16

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques LeCler ,  Laurent Moll

IPC: G06F12/08 ,  G06F12/10 ,  G06F17/50 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract translation: 系统TLB集成在互连中，使用并共享传输网络连接到共享步进端口。 事务能够通过第二发起方侧互连传递STLB分配信息，其中互连可以级联，以便允许发起者控制第一互连中的共享STLB。 在第一个互连中，多个STLB共享中间级转换缓存，当在两个STLB的请求之间存在局部性时，可提高性能。

公开(公告)号：US09141556B2

公开(公告)日：2015-09-22

申请号：US13969425

申请日：2013-08-16

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques LeCler ,  Philippe Boucard

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/08 ,  G06F17/50 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract translation: 系统TLB接受来自发起者的翻译预取请求。 Misses会向Walker端口生成外部翻译请求。 诸如ID，地址和类的请求的属性以及TLB的状态会影响多级翻译表中的翻译分配策略。 翻译表用SRAM实现，并组织成组。

公开(公告)号：US20140149687A1

公开(公告)日：2014-05-29

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而不进行修改或副作用。

公开(公告)号：US20150019776A1

公开(公告)日：2015-01-15

申请号：US13941537

申请日：2013-07-14

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Jean-Jacques Lecler ,  Jonah Proujansky-Bell ,  Philippe Boucard

IPC: G06F13/362

CPC classification number: G06F13/1605

Abstract: The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed.

Abstract translation: 本发明提供了一种用于半导体知识产权核心之间的交易接口。 待处理事务的紧急属性可以通过接口的特殊类型的事务来更改。 紧急性可以增加，至少提高一个指定的值，或者更改为指定的值。 对于具有多个待处理事务的接口，可以使用掩码来指示一个或多个ID，其事务应该更改。

公开(公告)号：US08930638B2

公开(公告)日：2015-01-06

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM Technologies, Inc.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而无需修改或副作用。

公开(公告)号：US09471538B2

公开(公告)日：2016-10-18

申请号：US13626758

申请日：2012-09-25

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler ,  Boris Boutillier

IPC: G06F15/78 ,  G06F13/364 ,  G06F11/07 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F11/0745 ,  G06F13/364 ,  G06F13/4059

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

公开(公告)号：US09882839B2

公开(公告)日：2018-01-30

申请号：US14720947

申请日：2015-05-25

Applicant: QUALCOMM Technologies Inc.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler

IPC: G06F3/00 ,  H04L12/28 ,  H04L12/935 ,  H04L12/709 ,  H04L12/801 ,  H04L12/933 ,  G06F13/40 ,  H04L29/06

CPC classification number: H04L49/3072 ,  G06F13/4009 ,  G06F2213/0038 ,  H04L45/245 ,  H04L47/10 ,  H04L49/109 ,  H04L69/22 ,  Y02B70/30 ,  Y02D50/30

Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

公开(公告)号：US09225665B2

公开(公告)日：2015-12-29

申请号：US13626766

申请日：2012-09-25

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler ,  Boris Boutillier

IPC: H04L12/933 ,  G06F12/12 ,  G06F15/78

CPC classification number: H04L49/109 ,  G06F12/126 ,  G06F15/7825

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract translation: 本发明是事务接口协议，其中接口协议在每个请求和响应信道中具有事务标识符信号。 它在目标网络接口单元（NIU）主机和通过事务接口直接连接的启动器NIU从站之间使用。 目标NIU响应信道使用事务ID信号来识别与相应请求相关联的上下文阵列中的条目。 目标NIU和启动器NIU的耦合使得能够形成包括多个片上网络（NoC）的片上互连，其中互连的拓扑更简单，更小，更快，并且具有更低的延迟。