公开(公告)号：US20180301463A1

公开(公告)日：2018-10-18

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20160093499A1

公开(公告)日：2016-03-31

申请号：US14869988

申请日：2015-09-29

Applicant: Renesas Electronics Corporation

Inventor： Kazuharu YAMABE ,  Shinichiro ABE ,  Shoji YOSHIDA ,  Hideaki YAMAKOSHI ,  Toshio KUDO ,  Seiji MURANAKA ,  Fukuo OWADA ,  Daisuke OKADA

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/28194 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract translation: 提供具有改进性能的半导体器件，同时提高半导体器件的制造步骤中的吞吐量。 在半导体衬底上形成由第一，第二，第三，第四和第五绝缘膜构成的绝缘膜部分。 第二绝缘膜是第一电荷存储膜，第四绝缘膜是第二电荷存储膜。 第一电荷储存膜含有硅和氮; 第三绝缘膜含有硅和氧; 并且第二电荷储存膜含有硅和氮。 第三绝缘膜的厚度小于第一电荷存储膜的厚度，并且第二电荷存储膜的厚度大于第一电荷存储膜的厚度。 第三绝缘膜通过用含水处理液处理第一电荷存储膜的上表面而形成。

公开(公告)号：US20200243545A1

公开(公告)日：2020-07-30

申请号：US16737571

申请日：2020-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI

IPC: H01L27/1157 ,  H01L29/423

Abstract: A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.

公开(公告)号：US20190279998A1

公开(公告)日：2019-09-12

申请号：US16278951

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Shinichiro ABE ,  Takashi HASHIMOTO ,  Yuto OMIZU

IPC: H01L27/11573 ,  H01L27/12 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

公开(公告)号：US20190363095A1

公开(公告)日：2019-11-28

申请号：US16404095

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU ,  Takashi HASHIMOTO ,  Hideaki YAMAKOSHI

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28 ,  H01L21/3065

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

公开(公告)号：US20180286881A1

公开(公告)日：2018-10-04

申请号：US15871818

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11568 ,  H01L27/11573 ,  G11C11/40

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

公开(公告)号：US20180090501A1

公开(公告)日：2018-03-29

申请号：US15709125

申请日：2017-09-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI

IPC: H01L27/108 ,  H01L27/12 ,  G11C7/10 ,  G11C11/4096 ,  G06F1/30

CPC classification number: H01L27/10852 ,  G06F1/30 ,  G11C7/1039 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4096 ,  G11C14/0018 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/1116 ,  H01L27/11573 ,  H01L27/1203

Abstract: A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or riot to apply the write voltage (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.

公开(公告)号：US20180047742A1

公开(公告)日：2018-02-15

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20180040365A1

公开(公告)日：2018-02-08

申请号：US15631101

申请日：2017-06-23

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI ,  Yoshiyuki ISHIGAKI ,  Toshiaki TAI ,  Hideaki YAMAKOSHI ,  Toshihiko HIROSE ,  Takuya ISHIDA

IPC: G11C11/417 ,  H01L23/535 ,  H01L21/265 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/4125 ,  H01L21/265 ,  H01L23/535 ,  H01L27/1104

Abstract: A semiconductor device which suppresses soft errors and functions as a non-volatile memory and a method for manufacturing the same. In the semiconductor device, a first non-volatile memory element and a second non-volatile memory element are electrically coupled to a first memory node and a second memory node through a first MOS transistor and a second MOS transistor respectively. A first capacitor and a second capacitor each have a storage node electrically coupled to the first memory node and the second memory node respectively and each have a cell plate to form a capacitance between the storage node and the cell plate.

公开(公告)号：US20140140133A1

公开(公告)日：2014-05-22

申请号：US14164761

申请日：2014-01-27

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Yasushi OKA ,  Daisuke OKADA

IPC: G11C16/04 ,  G11C5/06

CPC classification number: G11C16/0441 ,  G11C5/06 ,  G11C16/0433 ,  H01L27/11519 ,  H01L27/11521

Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device.A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.

Abstract translation: 为了提高具有非易失性存储器的半导体器件的性能。 进一步提高半导体器件的可靠性。 此外，为了提高半导体器件的性能以及提高半导体器件的可靠性。 每个由具有浮动栅极和与存储晶体管串联耦合的控制晶体管的存储晶体管构成的多个存储单元在半导体衬底的主表面上沿X方向和Y方向排列。 然后，在形成在半导体衬底上的多层布线结构的最下层布线层中设置有将在X方向排列的存储单元的存储晶体管的漏极区域连接的位线，并且位线布置成覆盖整个浮置 栅电极。