公开(公告)号：US20160240564A1

公开(公告)日：2016-08-18

申请号：US15139782

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

公开(公告)号：US20160043006A1

公开(公告)日：2016-02-11

申请号：US14882999

申请日：2015-10-14

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L21/8238 ,  H01L23/532 ,  H01L29/786

CPC classification number: H01L21/823828 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/53223 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

Abstract translation: 本发明使得可以增加形成在布线层中的有源元件中的栅极绝缘膜的选择性。 根据本发明的半导体器件具有使用在作为栅极线的布线层中的Al线上形成的抗反射膜的底栅型晶体管。

公开(公告)号：US20130200363A1

公开(公告)日：2013-08-08

申请号：US13738137

申请日：2013-01-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L27/105

CPC classification number: H01L29/7869 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/2436 ,  H01L29/22 ,  H01L29/24 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract translation: 提供了包括具有相互不同特性的两个晶体管的容易制造的半导体器件。 半导体器件包括衬底，设置在衬底上的多层布线层，设置在多层布线层中的第一晶体管，以及设置在不同于布置在多层布线层中的第一晶体管的层的层中的第二晶体管， 并具有与第一晶体管不同的特性。 这可以提供包括具有相互不同特性的两个晶体管的容易制造的半导体器件。

公开(公告)号：US20160027925A1

公开(公告)日：2016-01-28

申请号：US14875747

申请日：2015-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract translation: 半导体器件具有p型金属氧化物半导体层; 与p型金属氧化物半导体层连接的源电极; 与p型金属氧化物半导体层连接的漏电极; 以及与p型金属氧化物半导体层的一部分相对配置的栅电极。 栅电极和漏电极在顶视图中彼此分离。

公开(公告)号：US20150200135A1

公开(公告)日：2015-07-16

申请号：US14667915

申请日：2015-03-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20150349134A1

公开(公告)日：2015-12-03

申请号：US14822230

申请日：2015-08-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou Kaneko

IPC: H01L29/786 ,  H01L29/22 ,  H01L27/12 ,  H01L23/532 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L29/7869 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/2436 ,  H01L29/22 ,  H01L29/24 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract translation: 提供了包括具有相互不同特性的两个晶体管的容易制造的半导体器件。 半导体器件包括衬底，设置在衬底上的多层布线层，设置在多层布线层中的第一晶体管，以及设置在不同于布置在多层布线层中的第一晶体管的层的层中的第二晶体管， 并具有与第一晶体管不同的特性。 这可以提供包括具有相互不同特性的两个晶体管的容易制造的半导体器件。

公开(公告)号：US20130200472A1

公开(公告)日：2013-08-08

申请号：US13738217

申请日：2013-01-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20130181221A1

公开(公告)日：2013-07-18

申请号：US13710209

申请日：2012-12-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/12 ,  H01L27/1259 ,  H01L28/20 ,  H01L29/66742 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

Abstract: A circuit including an inverter is provided for a wiring layer.A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract translation: 为布线层设置包括逆变器的电路。 半导体器件设置有形成在绝缘膜上并且包括至少一个反相器元件的布线层电路。 逆变器设置有第一晶体管元件和电阻元件，其经由连接节点连接到第一晶体管。 第一晶体管元件设置有嵌入在包括绝缘膜的层间绝缘膜中的栅极电极，形成在层间绝缘膜和栅电极之上的栅极绝缘膜，以及形成在第一半导体层上的第一半导体层 源电极和漏电极之间的栅极绝缘膜。 电阻元件设置有用作电阻的第二半导体层。 第一半导体层和第二半导体层形成在同一层中。