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公开(公告)号：US20160190145A1
公开(公告)日：2016-06-30
申请号：US14972260
申请日：2015-12-17
Applicant: Renesas Electronics Corporation
Inventor： Keiichi MAEKAWA , Shoji YOSHIDA , Takashi TAKEUCHI , Hiroshi YANAGITA
IPC: H01L27/112
CPC classification number: H01L27/11206 , G11C17/12 , G11C17/16 , H01L23/5252
Abstract: A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.
Abstract translation: 半导体器件包括形成在SOI衬底上的SOI衬底和抗熔丝元件。 SOI衬底具有通过BOX层形成在支撑衬底的主表面侧的p型阱区和在p型阱区上形成的SOI层。 反熔丝元件具有通过玛瑙绝缘膜在SOI层上形成的栅电极。 反熔丝元件构成存储元件，并且在存储元件的写入操作中，向栅电极施加第一电位，并将与第一电位相同极性的第二电位施加到p型阱区。
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公开(公告)号：US20230093724A1
公开(公告)日：2023-03-23
申请号：US17876067
申请日：2022-07-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Atsushi AMO , Hiraku CHAKIHARA , Hiroshi YANAGITA , Akio ONO
Abstract: A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.
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公开(公告)号：US20160093555A1
公开(公告)日：2016-03-31
申请号：US14962556
申请日：2015-12-08
Applicant: Renesas Electronics Corporation
Inventor： Yasuhiro TAKEDA , Takao KUMIHASHI , Hiroshi YANAGITA , Takashi TAKEUCHI , Yasushi MATSUDA
IPC: H01L23/48 , H01L23/532 , H01L21/768
CPC classification number: H01L23/481 , H01L21/486 , H01L21/6836 , H01L21/76852 , H01L21/76898 , H01L22/14 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/0345 , H01L2224/0361 , H01L2224/0401 , H01L2224/05025 , H01L2224/05147 , H01L2224/05166 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05583 , H01L2224/05624 , H01L2224/05655 , H01L2224/06181 , H01L2224/11462 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/81192 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/00014 , H01L2924/12032 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/05552
Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
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公开(公告)号：US20130252416A1
公开(公告)日：2013-09-26
申请号：US13795731
申请日：2013-03-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yasuhiro TAKEDA , Takao KUMIHASHI , Hiroshi YANAGITA , Takashi TAKEUCHI , Yasushi MATSUDA
IPC: H01L21/48
CPC classification number: H01L23/481 , H01L21/486 , H01L21/6836 , H01L21/76852 , H01L21/76898 , H01L22/14 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/0345 , H01L2224/0361 , H01L2224/0401 , H01L2224/05025 , H01L2224/05147 , H01L2224/05166 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05583 , H01L2224/05624 , H01L2224/05655 , H01L2224/06181 , H01L2224/11462 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/81192 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/00014 , H01L2924/12032 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/05552
Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process.In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
Abstract translation: TSV技术作为多个半导体芯片的堆叠技术之一已经普及。 然而，本发明人已经公开，当使用所谓的第一通孔工艺，经由中间工艺，前通孔经由最后工艺等形成TSV时，存在诸如门击穿发生的缺陷的可能性 在随后的过程中进行静电击穿。 为了克服上述问题，本发明提供了一种制造半导体集成电路器件的方法，其中通孔形成在半导体衬底中形成孔，在孔中形成绝缘构件，并埋入 导电构件，同时用绝缘构件覆盖除了底部的孔的一部分。
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