公开(公告)号：US20240128248A1

公开(公告)日：2024-04-18

申请号：US18365455

申请日：2023-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI ,  Takayuki IGARASHI

IPC: H01L25/16 ,  H01F27/28 ,  H01F27/30 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01F27/2804 ,  H01F27/306 ,  H01L24/32 ,  H01F27/324 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2224/73265 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.

公开(公告)号：US20240014067A1

公开(公告)日：2024-01-11

申请号：US18319248

申请日：2023-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki ARIE ,  Takayuki IGARASHI

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L27/1203

Abstract: A semiconductor device having a semiconductor substrate, a BOX film on the semiconductor substrate, a semiconductor layer on the BOX film, a first trench penetrated through the semiconductor layer and reached to the first insulating film, a first insulating film covering a side surface of the first trench and in contact with an upper surface of the BOX film at a bottom of the first trench, a second trench formed at the bottom of the first trench such that the second trench penetrates through the first insulating film and reached in the BOX film, a second insulating film filled in the first trench and the second trench. A bottom surface of the second trench is located in the BOX film below an interface between the semiconductor layer and the BOX film, and a void is located in the second insulating film at the same height the interface.

公开(公告)号：US20200051913A1

公开(公告)日：2020-02-13

申请号：US16523685

申请日：2019-07-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko AIKA ,  Takayuki IGARASHI ,  Takehiro OCHI

IPC: H01L23/525 ,  H01L27/06 ,  H01L21/8234

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

公开(公告)号：US20230335487A1

公开(公告)日：2023-10-19

申请号：US18174942

申请日：2023-02-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L24/05 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73215

Abstract: An inductor to which a first potential is applied is surrounded by a first wiring connected with the inductor, and a pad connected with a second wiring, to which a second potential different from the first potential is applied, is disposed outside the second wiring such that the first wiring is surrounded by the second wiring.

公开(公告)号：US20170194164A1

公开(公告)日：2017-07-06

申请号：US15462583

申请日：2017-03-17

Applicant: Renesas Electronics Corporation

Inventor： Takuo FUNAYA ,  Takayuki IGARASHI

IPC: H01L21/3205 ,  H01L49/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

公开(公告)号：US20240170463A1

公开(公告)日：2024-05-23

申请号：US18511547

申请日：2023-11-16

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H01L25/10 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/5227 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137

Abstract: A second distance between a second lower inductor and a second upper inductor, which are components of a second transformer is smaller than a first distance between a first lower inductor and a first upper inductor which are components of a first transformer.

公开(公告)号：US20240105761A1

公开(公告)日：2024-03-28

申请号：US18358381

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H10N69/00 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L23/64 ,  H04B5/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F27/2828 ,  H01L23/5227 ,  H01L23/645 ,  H04B5/02 ,  H01F2017/0073 ,  H01F2017/0086

Abstract: A semiconductor chip includes a transformer that performs contactless communication between different potentials. The semiconductor chip includes a semiconductor substrate, a semiconductor region formed in an upper surface of the semiconductor substrate, and the transformer formed over the semiconductor substrate. Here, the transformer includes a lower inductor, a lead wiring portion electrically connected to the lower inductor, and an upper inductor 100 magnetically coupled to the lower inductor, and the lead wiring portion has a wiring facing the semiconductor region.

公开(公告)号：US20230010383A1

公开(公告)日：2023-01-12

申请号：US17835541

申请日：2022-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Hirokazu SAYAMA

IPC: H01L23/00

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

公开(公告)号：US20180337124A1

公开(公告)日：2018-11-22

申请号：US16048408

申请日：2018-07-30

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Takuo FUNAYA

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/06 ,  H01L27/12

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：US20180174900A1

公开(公告)日：2018-06-21

申请号：US15897561

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Yoshikazu TSUNEMINE ,  Takayuki IGARASHI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a manufacturing method thereof are provided. A discontinued part, in which the interface between an interlayer insulating film and a passivation film is discontinued, is formed between a first wiring layer and a second wiring layer that are adjacent to each other with a space therebetween. Both the interlayer insulating film and the passivation film face an air gap in the discontinued part.