公开(公告)号：US20220399281A1

公开(公告)日：2022-12-15

申请号：US17345399

申请日：2021-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/66 ,  H01L23/31 ,  H01L23/482 ,  H01L29/40 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

公开(公告)号：US20160035673A1

公开(公告)日：2016-02-04

申请号：US14878216

申请日：2015-10-08

Applicant: Renesas Electronics Corporation

Inventor： Takehiro UEDA

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

公开(公告)号：US20240363500A1

公开(公告)日：2024-10-31

申请号：US18307405

申请日：2023-04-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshimasa UCHINUMA ,  Takehiro UEDA

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/4952 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a first source electrode coupled to a first source terminal by a connection portion and having first and second slits on two opposite sides, a second source electrode coupled to a second source terminal, a Kelvin pad formed independently of the first source electrode, a power MOSFET coupled between the first source electrode and a drain terminal, a sense MOSFET coupled between the second source electrode and the drain terminal, a first wire coupled between a first source potential extraction port set at the first slit and the Kelvin pad, a second wire coupled between a second source potential extraction port set at the second slit and the Kelvin pad, wherein the connection portion has third and fourth slits corresponding to the first and second slits.

公开(公告)号：US20130026613A1

公开(公告)日：2013-01-31

申请号：US13630467

申请日：2012-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract translation: 一种切割包括第一导体和第二导体的电熔丝的方法，所述第一导体包括第一切割目标区域，所述第二导体从所述第一导体分支并连接到所述第一导体并且包括第二切割目标区域，所述第二切割目标区域是 形成在半导体衬底上，该方法包括使第一导体中的电流流动，使得第一导体的材料在连接第一导体与第二导体的耦合部分附近向外流动，以及切割第一切割目标区域和第二切割 目标区域。

公开(公告)号：US20230245941A1

公开(公告)日：2023-08-03

申请号：US18057326

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi AOKI ,  Takehiro UEDA

IPC: H01L23/31 ,  H01L21/02

CPC classification number: H01L23/3192 ,  H01L23/3171 ,  H01L21/022

Abstract: A semiconductor device includes an aluminum layer, a passivation film, and a protective film arranged between the aluminum layer and the passivation film. A plurality of aluminum regions are formed in the aluminum layer. A width of a gap between the adjacent aluminum regions is equal to or less than twice a thickness of the protective film 140. The gap is filled with the protective film 140.

公开(公告)号：US20210336017A1

公开(公告)日：2021-10-28

申请号：US16858276

申请日：2020-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA

IPC: H01L29/417 ,  H01L21/288 ,  C23C18/16

Abstract: The semiconductor device includes a first electrode, a second electrode electrically coupled to the first electrode, and a third electrodes electrically coupled to at least one of the first and the second electrode, a first plating deposition portion on the first electrode, a second and a third plating deposition portions formed on the second and the third electrode, respectively. The areas of the second and the third plating deposition portion are smaller than the area of the first plating deposition portion. The periphery length of the third plating deposition portion is longer than the periphery length of the second plating deposition portion.

公开(公告)号：US20190006500A1

公开(公告)日：2019-01-03

申请号：US15985987

申请日：2018-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA ,  Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265

CPC classification number: H01L29/7783 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/308 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

公开(公告)号：US20180159525A1

公开(公告)日：2018-06-07

申请号：US15797062

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Takehiro UEDA

IPC: H03K17/16 ,  H02M7/5387 ,  H02M1/34

CPC classification number: H03K17/168 ,  H02M1/34 ,  H02M7/53871 ,  H02M2001/346 ,  H03K2217/0045

Abstract: A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.

公开(公告)号：US20230062583A1

公开(公告)日：2023-03-02

申请号：US17463150

申请日：2021-08-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA

IPC: H01L29/78 ,  H01L27/02 ,  H01L23/522

Abstract: The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.

公开(公告)号：US20180286948A1

公开(公告)日：2018-10-04

申请号：US15889244

申请日：2018-02-06

Applicant: Renesas Electronics Corporation

Inventor： Takehiro UEDA

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/761 ,  H01L21/265

CPC classification number: H01L29/0688 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.