公开(公告)号：US20240234413A9

公开(公告)日：2024-07-11

申请号：US18452834

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Natsumi IKEDA ,  Tohru KAWAI

IPC: H01L27/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823475 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66492 ,  H01L29/7833

Abstract: A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.

公开(公告)号：US20230065925A1

公开(公告)日：2023-03-02

申请号：US17867768

申请日：2022-07-19

Applicant: Renesas Electronics Corporation.

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n−-type drain region and a gate electrode sandwich the n-type drift region in plan view.

公开(公告)号：US20170323890A1

公开(公告)日：2017-11-09

申请号：US15657690

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Masahiro SHIMIZU

IPC: H01L27/092 ,  G11C11/419

CPC classification number: H01L27/0928 ,  G11C11/419 ,  H01L27/1104 ,  H01L28/00

Abstract: A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.

公开(公告)号：US20240038888A1

公开(公告)日：2024-02-01

申请号：US18334763

申请日：2023-06-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7817 ,  H01L27/088 ,  H01L29/0615

Abstract: A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.

公开(公告)号：US20210109383A1

公开(公告)日：2021-04-15

申请号：US16601280

申请日：2019-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: G02F1/025 ,  G02F1/225 ,  H01L23/48

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

公开(公告)号：US20170170183A1

公开(公告)日：2017-06-15

申请号：US15359729

申请日：2016-11-23

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Masahiro SHIMIZU

IPC: H01L27/092 ,  G11C11/419

CPC classification number: H01L27/0928 ,  G11C11/419 ,  H01L27/1104 ,  H01L28/00

Abstract: A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.

公开(公告)号：US20160204099A1

公开(公告)日：2016-07-14

申请号：US14931991

申请日：2015-11-04

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract translation: 提高半导体器件的性能而不增加半导体芯片的面积尺寸。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件以半导体芯片的厚度方向层叠的方式配置。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。

公开(公告)号：US20240145553A1

公开(公告)日：2024-05-02

申请号：US18051935

申请日：2022-11-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: LDMOS having an n-type source region and a drain region formed on an upper surface of a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate dielectric film, and a field plate electrode formed on the semiconductor substrate between the gate electrode and the drain region via a dielectric film having a larger film thickness than the gate dielectric film, is formed. Here, the field plate electrode has a larger work function than an n-type semiconductor region formed in the semiconductor substrate directly below the field plate electrode.

公开(公告)号：US20240030131A1

公开(公告)日：2024-01-25

申请号：US18333033

申请日：2023-06-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eisuke KODAMA ,  Tohru KAWAI

IPC: H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/53271 ,  H01L23/53209

Abstract: An electric fuse including a fuse body and a fuse pad has a lamination structure of a polysilicon film and a cobalt silicide film. In the fuse body, a first portion having a first thickness and a second portion having a second thickness are formed. The first thickness is smaller than the second thickness. The polysilicon film is formed such that a thickness of the polysilicon film in the first portion becomes smaller than a thickness of the polysilicon film in the second portion.

公开(公告)号：US20220020668A1

公开(公告)日：2022-01-20

申请号：US16928872

申请日：2020-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: H01L23/485 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.