公开(公告)号：US20240370331A1

公开(公告)日：2024-11-07

申请号：US18649009

申请日：2024-04-29

Applicant: Rambus Inc.

Inventor： Taeksang SONG ,  John Eric LINSTADT ,  Steven C. WOO ,  Craig E. HAMPEL ,  Brent Steven HAUKNESS ,  Christopher HAYWOOD

IPC: G06F11/10

Abstract: A random access memory device includes memory cells in each row for storing metadata related to accesses to that row. These metadata dedicated memory cells may store counter values that may be updated (e.g., incremented or decremented) when certain events occur (e.g., activate row—ACT, column read—CAS, error detected, etc.). Which events cause an update of the metadata stored in a row, and under what conditions related to the metadata/count value (e.g., threshold, match, threshold value, etc.) cause further action to be taken (e.g., alert controller, set mode register, etc.) are configurable by a controller. Additional functions related to the metadata/counters are also configurable such as scanning counter values to determine the row address with highest or lowest value and pattern matching (e.g., process identification match/mismatch).

公开(公告)号：US20170338999A1

公开(公告)日：2017-11-23

申请号：US15616779

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Christopher HAYWOOD

IPC: H04L29/08 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L29/08027 ,  G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  H04L41/0806 ,  H04L69/324

Abstract: Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server system has a memory management module that is connected to a processor, a memory module, and a network interface. The memory management module is configured to allocate a first channel to access the memory module for local memory accesses by the processor and communicate first data blocks between the memory module and the processor. The memory management module determines that an amount of memory in the memory module is insufficient for an amount of memory needed by the processor, to allocate a second channel between the memory management module and the network interface to access a second memory module over a network for remote memory accesses by the processor. The memory management module communicates second data blocks between the memory management module and the network interface.

公开(公告)号：US20220277780A1

公开(公告)日：2022-09-01

申请号：US17696818

申请日：2022-03-16

Applicant: Rambus Inc.

Inventor： Christopher HAYWOOD ,  David WANG

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/07

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20190108101A1

公开(公告)日：2019-04-11

申请号：US16156953

申请日：2018-10-10

Applicant: Rambus Inc.

Inventor： Shih-ho WU ,  Christopher HAYWOOD

IPC: G06F11/14 ,  G06F12/02 ,  G06F3/06 ,  G06F11/16 ,  G11C14/00

Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.

公开(公告)号：US20240161795A1

公开(公告)日：2024-05-16

申请号：US18513473

申请日：2023-11-17

Applicant: Rambus Inc.

Inventor： Christopher HAYWOOD ,  David Wang

IPC: G11C7/10 ,  G06F11/07 ,  G06F11/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1006 ,  G11C29/52

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20230359554A1

公开(公告)日：2023-11-09

申请号：US18140441

申请日：2023-04-27

Applicant: Rambus Inc.

Inventor： Evan Lawrence ERICKSON ,  Christopher HAYWOOD

IPC: G06F12/02 ,  G06F12/0891

CPC classification number: G06F12/0292 ,  G06F12/0891 ,  G06F2212/401

Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

公开(公告)号：US20220310191A1

公开(公告)日：2022-09-29

申请号：US17722667

申请日：2022-04-18

Applicant: Rambus Inc.

Inventor： Christopher HAYWOOD

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/12 ,  G11C7/22 ,  G11C29/00

Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

公开(公告)号：US20240036726A1

公开(公告)日：2024-02-01

申请号：US18219842

申请日：2023-07-10

Applicant: Rambus Inc.

Inventor： Evan Lawrence ERICKSON ,  Christopher HAYWOOD

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0673

Abstract: A buffer/interface device of a memory node may read and compress fixed size blocks of data (e.g., pages). The size of each of the resulting compressed blocks of data is dependent on the data patterns in the original blocks of data. Fixed sized blocks of data are divided into fixed size sub-blocks (a.k.a., slots) for storing the resulting compressed blocks of data at with sub-block granularity. Pointers to the start of compressed pages are maintained at the final level of the memory node page tables in order to allow access to compressed pages. Upon receiving an access to a location within a compressed page, only the slots containing the compressed page need to be read and decompressed. The memory node page table entries may also include a content indicator (e.g., flag) that indicates whether any page within the block of memory associated with that page table entry is compressed.

公开(公告)号：US20220237126A1

公开(公告)日：2022-07-28

申请号：US17576398

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Christopher HAYWOOD ,  Evan Lawrence ERICKSON

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/455

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

公开(公告)号：US20220229567A1

公开(公告)日：2022-07-21

申请号：US17650643

申请日：2022-02-10

Applicant: Rambus, Inc.

Inventor： Shih-ho WU ,  Christopher HAYWOOD

IPC: G06F3/06 ,  G11C14/00

Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.