公开(公告)号：US12155391B2

公开(公告)日：2024-11-26

申请号：US18070713

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Catherine Chen

IPC: H03L7/081 ,  H03L7/097

Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

公开(公告)号：US12033683B2

公开(公告)日：2024-07-09

申请号：US17725026

申请日：2022-04-20

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Aws Shallal ,  Joey M. Esteves

IPC: G11C11/40 ,  G11C11/4074

CPC classification number: G11C11/4074

Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

公开(公告)号：US20240243662A1

公开(公告)日：2024-07-18

申请号：US18412966

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Cosmin Iorga ,  Panduka Wijetunga

IPC: H02M3/157 ,  H02M1/00

CPC classification number: H02M3/157 ,  H02M1/0019 ,  H02M1/0025 ,  H02M1/0064

Abstract: A DC-DC converter is disclosed. The DC-DC converter includes a sensing circuit having a first path to sense an output current of the DC/DC converter. A reference circuit generates a reference current to flow along a second path. The reference current is for comparison to the output current. A noise injection circuit couples to the second path and includes a replica circuit of the sensing circuit to sense the reference current. A differential amplifier rejects a common mode noise between the first path and the second path.

公开(公告)号：US20240055068A1

公开(公告)日：2024-02-15

申请号：US18266782

申请日：2021-12-08

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri ,  Panduka Wijetunga

IPC: G11C29/50 ,  G11C29/56

CPC classification number: G11C29/50012 ,  G11C29/56012 ,  G11C29/56004 ,  G11C2029/5602

Abstract: Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.

公开(公告)号：US11777546B2

公开(公告)日：2023-10-03

申请号：US17742679

申请日：2022-05-12

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga

IPC: H04M1/00 ,  H04B1/10 ,  H04B1/12

CPC classification number: H04B1/1027 ,  H04B1/1018 ,  H04B1/12

Abstract: A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.

公开(公告)号：US12147285B2

公开(公告)日：2024-11-19

申请号：US18077881

申请日：2022-12-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Panduka Wijetunga

IPC: G06F1/32 ,  G05F1/56 ,  G06F1/3206

Abstract: Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.

公开(公告)号：US11900985B1

公开(公告)日：2024-02-13

申请号：US17405527

申请日：2021-08-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Abhishek Desai

IPC: G11C11/4076 ,  G06F1/06 ,  H03K3/017

CPC classification number: G11C11/4076 ,  G06F1/06 ,  H03K3/017

Abstract: A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

公开(公告)号：US11782476B2

公开(公告)日：2023-10-10

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

CPC classification number: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US20220179444A1

公开(公告)日：2022-06-09

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US20250110540A1

公开(公告)日：2025-04-03

申请号：US18916160

申请日：2024-10-15

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Panduka Wijetunga

IPC: G06F1/3206 ,  G05F1/56

Abstract: Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.