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    Method and apparatus for performing bit-aligned permute
    1.
    发明申请
    Method and apparatus for performing bit-aligned permute 失效
    用于执行位对齐排列的方法和装置

    公开(公告)号：US20050139647A1

    公开(公告)日：2005-06-30

    申请号：US10745730

    申请日：2003-12-24

    申请人： Ramyanshu Datta ,  Robert Montoye

    发明人： Ramyanshu Datta ,  Robert Montoye

    IPC分类号： G06F1/00 ,  G06F7/76

    CPC分类号： G06F7/76

    摘要： A method and apparatus for performing bit-aligned permute are disclosed. A select register, a pair of data registers and a target register are provided. The entries of the select register is preloaded with a set of bit indices. Each of the bit indices points to a desired bit location within the data registers. The byte information stored in the data registers are then copied to the target register according to the bit indices within the select register.

    摘要翻译： 公开了一种用于执行位对齐排列的方法和装置。 提供一个选择寄存器，一对数据寄存器和一个目标寄存器。 选择寄存器的条目预先加载一组位索引。 每个比特索引指向数据寄存器内的所需比特位置。 存储在数据寄存器中的字节信息然后根据选择寄存器中的位索引被复制到目标寄存器。

    Shift-and-negate unit within a fused multiply-adder circuit
    2.
    发明申请
    Shift-and-negate unit within a fused multiply-adder circuit 失效
    融合乘法加法器电路中的移位和反相单元

    公开(公告)号：US20050144214A1

    公开(公告)日：2005-06-30

    申请号：US10745712

    申请日：2003-12-24

    申请人： Ramyanshu Datta ,  Robert Montoye

    发明人： Ramyanshu Datta ,  Robert Montoye

    IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/544

    CPC分类号： G06F5/012 ,  G06F7/5443

    摘要： A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and a group of data signals to generate a group of first intermediate signals. The coarse shift stage receives a second set of shift signals and the group of first intermediate signals to generate a group of second intermediate signals and their complement signals. The large shift stage and the coarse shift stage are executed within a first single processor cycle. The negate stage receives a complement decision signal and the group of second intermediate signals along with their complement signals to generate a group of third intermediate signals. Finally, the fine shift stage receives a third set of shift signals and the group of third intermediate signals to generate a group of output signals. The negate stage and the fine shift stage are executed within a second single processor cycle.

    摘要翻译： 公开了一种融合乘法加法器电路内的低功率移相和无效单元。 移位和否定单元包括大的移位阶段，粗调班级，否定阶段和精细班级。 大移位级接收第一组移位信号和一组数据信号以产生一组第一中间信号。 粗移位级接收第二组移位信号和第一中间信号组，以产生一组第二中间信号及其补码信号。 在第一单个处理器周期内执行大移位级和粗移位级。 否定阶段接收补码判定信号和第二中间信号组及其补码信号以产生一组第三中间信号。 最后，精细移位级接收第三组移位信号和第三中间信号组，以产生一组输出信号。 否定阶段和精细转换阶段在第二个单个处理器周期内执行。

    4-to-2 carry save adder using limited switching dynamic logic
    3.
    发明申请
    4-to-2 carry save adder using limited switching dynamic logic 失效
    使用有限切换动态逻辑的4对2进位保存加法器

    公开(公告)号：US20050102345A1

    公开(公告)日：2005-05-12

    申请号：US10702989

    申请日：2003-11-06

    申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

    发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

    IPC分类号： G06F7/50 ,  G06F7/60

    CPC分类号： G06F7/607

    摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

    摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

    Computing carry-in bit to most significant bit carry save adder in current stage
    4.
    发明申请
    Computing carry-in bit to most significant bit carry save adder in current stage 失效
    计算进位位到当前阶段的最高有效位进位保存加法器

    公开(公告)号：US20050102346A1

    公开(公告)日：2005-05-12

    申请号：US10702992

    申请日：2003-11-06

    申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

    发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

    IPC分类号： G06F7/50 ,  G06F7/60

    CPC分类号： G06F7/607

    摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

    摘要翻译： 一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。 进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位 前一阶段 通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟 由高阶全加器。

    Skewed inverter delay line for use in measuring critical paths in an integrated circuit
    6.
    发明授权
    Skewed inverter delay line for use in measuring critical paths in an integrated circuit 失效
    用于测量集成电路中关键路径的偏转逆变器延迟线

    公开(公告)号：US07260755B2

    公开(公告)日：2007-08-21

    申请号：US11071554

    申请日：2005-03-03

    申请人： Gary Dale Carpenter ,  Ramyanshu Datta

    发明人： Gary Dale Carpenter ,  Ramyanshu Datta

    IPC分类号： G01R31/28 ,  G06K5/04 ,  H03M13/00

    CPC分类号： G01R31/31725 ,  G01R31/3016

    摘要： An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay between the delay path input and output signal transitions. A delay line receives the pulse signal from the pulse generator. The delay line generates information indicative of the pulse signal pulse width. The delay line may include multiple stages in series where each stage reduces the pulse width of the pulse signal. The delay line may include a high skew inverter having PMOS and NMOS transistors having significantly different gains. The pulse generator is configured to produce a positive going pulse signal regardless of whether the delay path is inverting or non-inverting.

    摘要翻译： 集成电路包括可测试延迟路径。 延迟路径输入信号的转变导致延迟路径输出信号的随后转变。 脉冲发生器接收延迟路径输入和输出信号并产生具有指示延迟路径输入和输出信号转换之间的延迟的脉冲宽度的脉冲信号。 延迟线从脉冲发生器接收脉冲信号。 延迟线产生指示脉冲信号脉冲宽度的信息。 延迟线可以包括串联的多个级，其中每级降低脉冲信号的脉冲宽度。 延迟线可以包括具有PMOS和NMOS晶体管的具有显着不同增益的高偏斜反相器。 脉冲发生器被配置为产生正向脉冲信号，而不管延迟路径是反相还是反相。

    Computing carry-in bit to most significant bit carry save adder in current stage
    7.
    发明授权
    Computing carry-in bit to most significant bit carry save adder in current stage 失效
    计算进位位到当前阶段的最高有效位进位保存加法器

    公开(公告)号：US07216141B2

    公开(公告)日：2007-05-08

    申请号：US10702992

    申请日：2003-11-06

    申请人： Wendy A. Belluomini ,  Ramyanshu Datta ,  Jente Benedict Kuang ,  Chandler T. McDowell ,  Robert K. Montoye ,  Hung C. Ngo

    发明人： Wendy A. Belluomini ,  Ramyanshu Datta ,  Jente Benedict Kuang ,  Chandler T. McDowell ,  Robert K. Montoye ,  Hung C. Ngo

    IPC分类号： G06F7/50

    CPC分类号： G06F7/607

    摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

    摘要翻译： 一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。 进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位 前一阶段 通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟 由高阶全加器。

    4-to-2 carry save adder using limited switching dynamic logic
    8.
    发明授权
    4-to-2 carry save adder using limited switching dynamic logic 失效
    使用有限切换动态逻辑的4对2进位保存加法器

    公开(公告)号：US07284029B2

    公开(公告)日：2007-10-16

    申请号：US10702989

    申请日：2003-11-06

    申请人： Wendy A. Belluomini ,  Ramyanshu Datta ,  Chandler T. McDowell ,  Robert K. Montoye ,  Hung C. Ngo

    发明人： Wendy A. Belluomini ,  Ramyanshu Datta ,  Chandler T. McDowell ,  Robert K. Montoye ,  Hung C. Ngo

    IPC分类号： G06F7/50

    CPC分类号： G06F7/607

    摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

    摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

    Method and apparatus for performing bit-aligned permute
    9.
    发明授权
    Method and apparatus for performing bit-aligned permute 失效
    用于执行位对齐排列的方法和装置

    公开(公告)号：US07014122B2

    公开(公告)日：2006-03-21

    申请号：US10745730

    申请日：2003-12-24

    申请人： Ramyanshu Datta ,  Robert Kevin Montoye

    发明人： Ramyanshu Datta ,  Robert Kevin Montoye

    IPC分类号： G06K19/06

    CPC分类号： G06F7/76

    摘要： A method and apparatus for performing bit-aligned permute are disclosed. A select register, a pair of data registers and a target register are provided. The entries of the select register is preloaded with a set of bit indices. Each of the bit indices points to a desired bit location within the data registers. The byte information stored in the data registers are then copied to the target register according to the bit indices within the select register.

    摘要翻译： 公开了一种用于执行位对齐排列的方法和装置。 提供一个选择寄存器，一对数据寄存器和一个目标寄存器。 选择寄存器的条目预先加载一组位索引。 每个比特索引指向数据寄存器内的所需比特位置。 存储在数据寄存器中的字节信息然后根据选择寄存器中的位索引被复制到目标寄存器。