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    Through carrier dual side loop-back testing of TSV die after die attach to substrate
    3.
    发明授权
    Through carrier dual side loop-back testing of TSV die after die attach to substrate 有权
    通过载体双端回路测试TSV裸片裸片附着于基板上

    公开(公告)号：US08344749B2

    公开(公告)日：2013-01-01

    申请号：US12795376

    申请日：2010-06-07

    申请人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    发明人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2886 ,  G01R31/2896

    摘要： A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

    摘要翻译： 一种测试电子组件的方法，包括在衬底载体上附着到ML封装衬底上的分离的TSV芯片。 衬底载体包括用于允许探针接触耦合到TSV的前侧的封装衬底的底部上的BGA衬底焊盘的通孔。 TSV管芯底部的可接触的TSV尖端与顶侧耦合器接触，顶侧耦合器包括与TSV端头的至少一部分的布局匹配的耦合端子的图案，耦合到TSV端头的焊盘。 顶侧耦合器电连接成对的耦合端子以提供多个TSV回环路径。 BGA衬底焊盘与延伸穿过通孔的多个探针尖端接触以耦合到TSV的前侧。 在电子组件上执行电气测试以获得至少一个测试参数。

    THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE
    4.
    发明申请
    THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE 有权
    通过搬运到底板后的TSV DIE的运输双面环回测试

    公开(公告)号：US20110298488A1

    公开(公告)日：2011-12-08

    申请号：US12795376

    申请日：2010-06-07

    申请人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    发明人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    IPC分类号： G01R31/02 ,  G01R1/067 ,  G01R31/26

    CPC分类号： G01R31/2886 ,  G01R31/2896

    摘要： A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

    摘要翻译： 一种测试电子组件的方法，包括在衬底载体上附着到ML封装衬底上的单独的TSV裸片。 衬底载体包括用于允许探针接触耦合到TSV的前侧的封装衬底的底部上的BGA衬底焊盘的通孔。 TSV管芯底部的可接触的TSV尖端与顶侧耦合器接触，顶侧耦合器包括匹配终端的图案，该图案匹配TSV尖端的至少一部分的布局或耦合到TSV尖端的焊盘。 顶侧耦合器电连接成对的耦合端子以提供多个TSV回环路径。 BGA衬底焊盘与延伸穿过通孔的多个探针尖端接触以耦合到TSV的前侧。 在电子组件上执行电气测试以获得至少一个测试参数。

    Probe card assembly for high density integrated circuits
    7.
    发明授权
    Probe card assembly for high density integrated circuits 失效
    用于高密度集成电路的探头卡组件

    公开(公告)号：US5828226A

    公开(公告)日：1998-10-27

    申请号：US746117

    申请日：1996-11-06

    申请人： H. Dan Higgins ,  Rajiv Pandey ,  Norman J. Armendariz ,  R. Dennis Bates

    发明人： H. Dan Higgins ,  Rajiv Pandey ,  Norman J. Armendariz ,  R. Dennis Bates

    IPC分类号： G01R1/073

    CPC分类号： G01R1/07378

    摘要： A probe card assembly includes a probe card, an interposer and a probe array. The probe array includes a plurality of closely spaced pins, each pin includes a post and a beam, and each beam has a first end attached to the top of a post and a second end for contacting an integrated circuit. A bead on the second end of the beam assures that the free end of the beam will contact an IC first. For contacts on a grid, the beams extend diagonally relative to the rows and columns of the grid, enabling the beams to be longer. For contacts in a row on centers closer than the pins, two rows of pins straddle the contacts and the beams extend toward the contacts from opposite sides of the contacts. The probe array can be formed on the high density side of the interposer.

    摘要翻译： 探针卡组件包括探针卡，插入器和探针阵列。 探针阵列包括多个紧密间隔的销，每个销包括柱和梁，并且每个梁具有连接到柱的顶部的第一端和用于接触集成电路的第二端。 梁的第二端上的小珠确保梁的自由端首先与IC接触。 对于栅格上的触点，光束相对于栅格的行和列倾斜延伸，使得光束更长。 对于比引脚更靠近的中心的一行中的触点，两排销跨接触点，并且梁从触头的相对侧朝向触点延伸。 探针阵列可以形成在插入件的高密度侧上。