公开(公告)号：US08575697B2

公开(公告)日：2013-11-05

申请号：US13039167

申请日：2011-03-02

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: H01L27/11 ,  H01L27/12 ,  G11C5/06 ,  G11C11/00

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

Abstract translation: 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US08432216B2

公开(公告)日：2013-04-30

申请号：US13007483

申请日：2011-01-14

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC classification number: H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

Abstract: The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

Abstract translation: 本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。 数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区 渠道区域。 特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。 而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

公开(公告)号：US08310866B2

公开(公告)日：2012-11-13

申请号：US12168671

申请日：2008-07-07

Applicant: Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

Inventor： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC: G11C11/02 ,  G11C7/00 ,  H01L21/00

CPC classification number: G11C7/04 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

Abstract translation: 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。

公开(公告)号：US08305803B2

公开(公告)日：2012-11-06

申请号：US12942754

申请日：2010-11-09

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C11/40 ,  G11C11/402

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0711 ,  H01L27/10802 ,  H01L29/086 ,  H01L29/7302

Abstract: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

Abstract translation: 本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。 注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。 具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。 本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

公开(公告)号：US20110241157A1

公开(公告)日：2011-10-06

申请号：US12793515

申请日：2010-06-03

Applicant: Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

Abstract translation: 本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案， 通过分子键合供体和手柄底物以获得供体 - 处理化合物。

公开(公告)号：US07994560B2

公开(公告)日：2011-08-09

申请号：US12173702

申请日：2008-07-15

Applicant: Christian Caillat ,  Richard Ferrant

Inventor： Christian Caillat ,  Richard Ferrant

IPC: H01L29/94

CPC classification number: H01L27/10823 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/1203

Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

Abstract translation: 集成电路包括衬底和至少一个有源区。 在与基板分离的有源区中产生的晶体管。 该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。 栅极结构位于所述通道的顶部并且用于控制通道。 栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。 电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。 该电容器也形成在沟槽中。 电极线连接到电容器的第一电极。 电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。 位线位于门结构下方。 集成电路例如可以是DRAM存储单元。

公开(公告)号：US20110133822A1

公开(公告)日：2011-06-09

申请号：US13013580

申请日：2011-01-25

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC classification number: H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

Abstract translation: 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅极控制区域的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：US06995997B2

公开(公告)日：2006-02-07

申请号：US10862057

申请日：2004-06-04

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

Abstract translation: 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

公开(公告)号：US20050174873A1

公开(公告)日：2005-08-11

申请号：US11096970

申请日：2005-04-01

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C20060101 ,  G11C8/00 ,  G11C11/00 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4097

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

公开(公告)号：US20050157534A1

公开(公告)日：2005-07-21

申请号：US10627955

申请日：2003-07-25

Applicant: Richard Ferrant ,  Francois Jacquet

Inventor： Richard Ferrant ,  Francois Jacquet

IPC: G11C11/406 ,  G11C11/24

CPC classification number: G11C11/406

Abstract: A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

Abstract translation: 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。