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公开(公告)号：US06791081B1
公开(公告)日：2004-09-14
申请号：US10109517
申请日：2002-03-27
IPC分类号： G01B528
CPC分类号： G01Q60/24 , G01N15/088 , Y10S977/852
摘要： A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.
摘要翻译： 使用原子力显微镜（AFM）提供了一种测量纳米多孔材料孔隙率的方法。 使用AFM创建具有亚原子分辨率的表面拓扑图，其中孔形状和尺寸可以通过测量与顶部或断裂面相交的孔来确定。 对于需要更精确测量的多孔材料，使用扫描速度慢的微小扫描区域和精细的AFM尖端，并且可以从样品区域进行一般的分布估计。
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2.发明申请SEMICONDUCTOR DIE INTERCONNECT FORMED BY AEROSOL APPLICATION OF ELECTRICALLY CONDUCTIVE MATERIAL 审中-公开气溶胶应用电导体材料形成的半导体DIE互连公开(公告)号：US20100140811A1
公开(公告)日：2010-06-10
申请号：US12634598
申请日：2009-12-09
CPC分类号： H01L24/76 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/76155 , H01L2224/82007 , H01L2224/82102 , H01L2225/06551 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.
摘要翻译： 通过以气溶胶形式施加导电材料，例如通过气溶胶喷射印刷，在半导体管芯上形成互连端子。 而且，通过施加与气泡形式的导电材料，与模具上的焊盘或模具上的焊盘接触，形成堆叠裸片之间或芯片之间的电互连，以及下层支撑件（例如封装衬底）中的电路之间的电互连 基板，并在相应的焊盘之间通过。 在一些实施例中，在由模具的互连侧壁形成的内角处形成圆角，并且在底层特征（下面的模具或支撑件）上的垫的表面内侧形成圆角; 并且导电材料经过圆角的表面。
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3.发明申请公开(公告)号：US20090072234A1
公开(公告)日：2009-03-19
申请号：US12313089
申请日：2008-11-17
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
摘要翻译： 在本发明的电子测试结构中，提供了覆盖基板的导体。 电子器件覆盖导体的一部分，并且包括连接到导体的第一电极，第二电极和在第一和第二电极之间的绝缘层。 导体的一部分被暴露以便进入其中。
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公开(公告)号：US20080128691A1
公开(公告)日：2008-06-05
申请号：US11633930
申请日：2006-12-05
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
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5.发明授权Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures 有权在铜上利用含Ta的盖以促进铜通孔和记忆元件结构的同时形成公开(公告)号：US07232765B1
公开(公告)日：2007-06-19
申请号：US10988239
申请日：2004-11-12
申请人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
发明人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76849 , H01L21/7685 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L51/0021
摘要： Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.
摘要翻译： 公开了促进铜通孔和记忆元件结构的同时形成的方法。 所述方法包括在金属线上形成通孔并形成铜塞，其中铜塞包括记忆元件膜形成铜塞（memE铜塞）和形成铜塞（非memE铜塞）的非存储元件，形成含钽 覆盖非memE铜插头的上表面，并沉积存储元件膜。 含钽盖防止在非memE铜插头中形成记忆元件膜。 本发明有利地有助于半导体器件的成本有效的制造。
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6.发明授权公开(公告)号：US06870183B2
公开(公告)日：2005-03-22
申请号：US10287612
申请日：2002-11-04
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.
摘要翻译： 本发明提供一种多层有机存储器件，其可以作为其中构造有多个堆叠和/或并行存储器结构的非易失性存储器件来操作。 可以在两个或多个电极之间形成多单元和多层有机存储器组件，所述两个或更多个电极在形成各个单元的电极之间具有选择性导电介质，同时利用分隔组件使得能够堆叠额外的存储器单元， 以前形成的细胞。 可以通过添加额外的层 - 通过附加分隔部件分开的相应层来形成存储器堆叠，其中可以并行形成多个堆叠以提供高密度存储器件。
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7.发明授权公开(公告)号：US06852586B1
公开(公告)日：2005-02-08
申请号：US10677042
申请日：2003-10-01
IPC分类号： G11C13/02 , H01L27/28 , H01L51/40 , H01L21/8234
CPC分类号： G11C13/0069 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2013/009 , G11C2213/56 , G11C2213/71 , H01L27/28 , H01L51/0012
摘要： The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that a shortest conductive path can be achieved. The method includes depositing a concentrated solution of conducting polymer on a conductive surface, applying heat and optionally a vacuum, and permitting the conducting polymer to self-assemble into an organic semiconductor. The organic semiconductor can be employed within single and multi-cell memory devices by forming a structure with two or more electrodes while employing the organic semiconductor along with a passive device between the electrodes. A partitioning component can be integrated with the memory device to facilitate programming and stacking of additional memory cells on top of or in association with previously formed cells.
摘要翻译： 本发明提供可用作存储单元的选择性导电的有机半导体（例如，聚合物）器件。 包括导电聚合物的聚合物溶液相对于导电电极自组装。 该过程提供自组装，使得可以实现最短的导电路径。 该方法包括将导电聚合物的浓缩溶液沉积在导电表面上，施加热量和任选的真空，并允许导电聚合物自组装成有机半导体。 有机半导体可以在单电池和多电池存储器件中使用，通过形成具有两个或多个电极的结构，同时在电极之间使用有机半导体以及无源器件。 分区组件可以与存储器件集成，以便于在先前形成的单元之上或与之前相关联的附加存储器单元的编程和堆叠。
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公开(公告)号：US06836017B2
公开(公告)日：2004-12-28
申请号：US10759170
申请日：2004-01-20
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。
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9.发明授权公开(公告)号：US06756672B1
公开(公告)日：2004-06-29
申请号：US09776750
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
发明人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 通孔也可以有圆角。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由碳化硅形成。 还公开了制造半导体器件的方法。
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公开(公告)号：US06713382B1
公开(公告)日：2004-03-30
申请号：US10059268
申请日：2002-01-31
申请人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
发明人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.
摘要翻译： 一种制造半导体器件的方法包括形成第一层，在第一层上形成第一势垒层，在第一阻挡层上形成电介质层，形成通过介电层的侧表面的开口，蚀刻第一阻挡层， 并用金属填充开口以形成第一金属特征。 该方法还包括在侧表面上置换羟基封端的离子的步骤。 取代羟基封端的离子的该步骤可以在形成开口之后或在第一阻挡层被蚀刻之后发生。 还公开了通过制造方法制造的半导体器件。
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