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    NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD
    1.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD 有权
    非易失性存储器件和编程方法

    公开(公告)号：US20140269057A1

    公开(公告)日：2014-09-18

    申请号：US14211077

    申请日：2014-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOAV SHERESHEVSKI ,  AVNER DOR ,  SHMUEL DASHEVSKY ,  JUN JIN KONG ,  PIL SANG YOON

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459

    Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.

    Abstract translation: 非易失性存储器件的编程方法包括： 定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数 编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME 审中-公开

    公开(公告)号：US20190050343A1

    公开(公告)日：2019-02-14

    申请号：US15671855

    申请日：2017-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： ELONA EREZ ,  AVNER DOR ,  JUN-JIN KONG

    IPC: G06F12/1009 ,  G06F3/06

    Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

    FLASH MEMORY DEVICE INCLUDING DEDUPLICATION, AND RELATED METHODS
    4.
    发明申请
    FLASH MEMORY DEVICE INCLUDING DEDUPLICATION, AND RELATED METHODS 有权

    公开(公告)号：US20170160978A1

    公开(公告)日：2017-06-08

    申请号：US14956715

    申请日：2015-12-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： ELONA EREZ ,  AVNER DOR ,  JUN JIN KONG

    IPC: G06F3/06

    CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/00 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10

    Abstract: A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device. The difference between the write data sector and its respective paired data sector is stored in an unoccupied portion of the corresponding physical page of the flash memory device.

    LOW POWER ECC FOR EUFS
    6.
    发明申请
    LOW POWER ECC FOR EUFS 有权

    公开(公告)号：US20210376859A1

    公开(公告)日：2021-12-02

    申请号：US16885772

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： AVNER DOR ,  Amit Berman ,  Ariel Doubchak

    IPC: H03M13/13 ,  H03M13/11 ,  H03M13/29 ,  G06F7/544

    Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

    FLASH MEMORY DEVICE INCLUDING ADDRESS MAPPING FOR DEDUPLICATION, AND RELATED METHODS
    7.
    发明申请
    FLASH MEMORY DEVICE INCLUDING ADDRESS MAPPING FOR DEDUPLICATION, AND RELATED METHODS 审中-公开

    公开(公告)号：US20170161202A1

    公开(公告)日：2017-06-08

    申请号：US14957114

    申请日：2015-12-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： ELONA EREZ ,  AVNER DOR ,  JUN JIN KONG

    IPC: G06F12/10 ,  G06F12/02

    CPC classification number: G06F12/10 ,  G06F3/06 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207

    Abstract: A data storage device includes a flash memory that includes blocks of physical pages that include physical sectors configured to store data therein. A memory control unit, including a flash translation layer (FTL), is configured to receive write data sectors to be stored in the flash memory, determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation, and store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory. Logical-to-physical addresses of the reference data sector and the corresponding matched data sector are mapped in the FTL, and physical-to-logical information regarding the corresponding matched data sector is written in a designated physical-to-logical information area of the flash memory. The physical-to-logical information area may be a metadata area of a physical sector, an adjacent physical sector in a same page, a last sector of a block or a dedicated block of the flash memory.

    MEMORY CONTROLLER, METHOD OF OPERATING THE SAME, AND SYSTEM INCLUDING THE SAME
    8.
    发明申请
    MEMORY CONTROLLER, METHOD OF OPERATING THE SAME, AND SYSTEM INCLUDING THE SAME 有权
    存储器控制器，其操作方法和包括其的系统

    公开(公告)号：US20140281827A1

    公开(公告)日：2014-09-18

    申请号：US14208340

    申请日：2014-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MOSHE TWITTO ,  AVNER DOR ,  JUN JIN KONG ,  Chang Kyu SEOl ,  HONG RAK SON

    IPC: G06F11/10

    CPC classification number: G06F11/1072 ,  G06F11/108

    Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

    Abstract translation: 使用存储器控制器处理数据的方法包括基于每个多级单元的当前单元状态来确定可以改变多个多电平单元中的每一个的至少一个单元状态，其中每个多电平单元 包括多个数据页; 当数据页的值基于映射到所述至少一个单元状态的映射值具有单个映射值并且生成关于所述卡位的卡位位数据时，将所述数据页之一确定为具有卡住位; 以及基于所述卡住的位数据对要存储在所述多级单元中的写入数据进行编码。

    LOW-POWER ERROR CORRECTION CODE COMPUTATION IN GF (2R)
    9.
    发明申请
    LOW-POWER ERROR CORRECTION CODE COMPUTATION IN GF (2R) 有权

    公开(公告)号：US20220021401A1

    公开(公告)日：2022-01-20

    申请号：US16929983

    申请日：2020-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： AVNER DOR ,  Amit Berman ,  Ariel Doubchak ,  Elik Almog Sheffi ,  Yaron Shany

    IPC: H03M13/15 ,  H03M13/00

    Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ω=Σ0≤i≤r−1βi×αi wherein α is a fixed primitive element of F, and βi∈GF(2), wherein K=GF(2s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω1+α×ω2, ω1=Σ0≤i≤s−1γi×δi∈K, ω2=Σ0≤i≤s−1γi+s×δi∈K, and γ=[γ0, . . . , γr−1]T∈GF(2)r; accessing a first table with ω1 to obtain ω3=ω1−1, computing ω2×ω3 in field K, accessing a second table with ω2=ω3 to obtain (1+α×ω2×ω3)−1=ω4+α×ω5, wherein ω−1=(ω1×(1+α×ω2×ω3))−1=ω3×(ω4+α×ω5)=ω3×ω4+α×ω3×ω5; and computing products ω3×ω4 and ω3×ω5 to obtain ω−1=Σ0≤i≤s−1θi×δi+α·Σi≤i≤s−1θi+s=δi where θi∈GF(2).

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