Abstract:
A decoding method for an iterative message-passing based decoder, such as a low-density parity-check (LDPC) decoder, includes calculating syndrome information for a received word, and initializing variable nodes based on the received word. Each received bit of the received word may be represented by a Likelihood-Ratio (LR) or Log-Likelihood-Ratio (LLR) at a respective variable node. Further, the method includes iteratively updating check nodes, and updating the LRs of variable nodes using the syndrome information, determining an error vector from the LRs of the variable nodes, and determining a transmitted word, corresponding to the received word, by subtracting the error vector from the received word. The syndrome information is calculated based upon a parity check matrix.
Abstract:
A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.
Abstract:
A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n−kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns and Tj has k1−{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I ) ( a b ) = ( Q j | T j ) s ~ = T j s where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.
Abstract:
A method of correcting values errantly attributed to bits of error correction code (ECC) blocks during a read operation. The method includes, upon determining that an error exists in the jth bit of one or more of the ECC blocks: 1) retrieving an estimate of the voltage value stored by the nonvolatile memory cell corresponding to the jth bit of each of the ECC blocks having errant data; 2) identifying, among the voltage value estimates retrieved in operation (1), an ECC block whose corresponding voltage value estimate retrieved in operation (1) is closest to the voltage value of a decision boundary for determining whether to assign a bit value of “0” or “1” to the jth bit of the ECC blocks; and 3) inverting the value of the jth bit of the ECC block identified in operation (2).
Abstract:
A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.
Abstract:
Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.
Abstract:
A method of operating a memory device comprises programming a first data signal to a first memory cell, attempting to program a second data signal to the first memory cell in a state where the first memory cell is not erased, and marking the first memory cell as blank upon failing to program the second data signal to the first memory cell.