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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11699992B2

    公开(公告)日：2023-07-11

    申请号：US16726379

    申请日：2019-12-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

    IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

    CPC classification number: H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

    Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11362032B2

    公开(公告)日：2022-06-14

    申请号：US16919670

    申请日：2020-07-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Changbeom Kim ,  Dalhee Lee ,  Eun-Hee Choi

    IPC: H01L21/00 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L27/092 ,  H01L27/02 ,  H01L27/118 ,  H01L29/423

    Abstract: A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

    STANDARD CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
    5.
    发明申请
    STANDARD CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20230077532A1

    公开(公告)日：2023-03-16

    申请号：US17946761

    申请日：2022-09-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wookyu KIM ,  Changbeom Kim ,  Taejun Yoo ,  Seungmin Lee

    IPC: G06F30/392 ,  G06F30/394 ,  G06F30/327

    Abstract: A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.

    High-speed flip flop circuit including delay circuit
    6.
    发明授权
    High-speed flip flop circuit including delay circuit 有权

    公开(公告)号：US11509295B2

    公开(公告)日：2022-11-22

    申请号：US17340215

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Changbeom Kim ,  Dalhee Lee ,  Wookyu Kim

    IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/3562

    Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

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