公开(公告)号：US11917819B2

公开(公告)日：2024-02-27

申请号：US17359771

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Geunwon Lim ,  Jisung Cheon

IPC: H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L21/311

CPC classification number: H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L21/31111 ,  H01L21/31116

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US11640922B2

公开(公告)日：2023-05-02

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US11587940B2

公开(公告)日：2023-02-21

申请号：US16412875

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon Lim ,  Jaehoon Shin ,  Myungkeun Lee

IPC: H01L27/11556 ,  H01L29/792 ,  H01L27/11582

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, first to fourth stack structures spaced apart in a first direction on the second substrate, first and second support connectors between the second and third stack structures, third and fourth support connectors between the third and fourth stack structures, and a through dielectric pattern penetrating the first stack structure and the second substrate. A first distance between the first and second support connectors is different from a second distance between the third and fourth support connectors.

公开(公告)号：US12178043B2

公开(公告)日：2024-12-24

申请号：US17232500

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim

IPC: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A nonvolatile memory device may include a substrate; a first stacked structure on the substrate; a second stacked structure on the first stacked structure; a channel structure including a first portion passing through the first stacked structure and a second portion passing through the second stacked structure; and a filling structure including a first portion passing through the first stacked structure and extending in a first horizontal direction and a second portion passing through the second stacked structure and extending in the first horizontal direction. The upper end of the first portion of the filling structure may be at a same height as the upper end of the first portion of the channel structure.

公开(公告)号：US12021022B2

公开(公告)日：2024-06-25

申请号：US17645866

申请日：2021-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/50

CPC classification number: H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor device includes a substrate having a cell array region and a pad region, a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region, first separation regions penetrating the stack structure in the pad region, extending in a first direction, and including first and second dummy insulating layers, the first dummy insulating layers covering side walls of the first separation regions and including horizontal portions covering portions of the gate electrodes, and the second dummy insulating layers disposed between the first dummy insulating layers, extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction, second separation regions dividing the stack structure and extending in the first direction, and cell contact plugs penetrating the horizontal portions and connected to the gate electrodes.

公开(公告)号：US20230232632A1

公开(公告)日：2023-07-20

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11637121B2

公开(公告)日：2023-04-25

申请号：US16802736

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11233004B2

公开(公告)日：2022-01-25

申请号：US16732772

申请日：2020-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim

IPC: H01L27/11578 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11556

Abstract: A semiconductor device includes a substrate having a cell array region and a pad region, a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region, first separation regions penetrating the stack structure in the pad region, extending in a first direction, and including first and second dummy insulating layers, the first dummy insulating layers covering side walls of the first separation regions and including horizontal portions covering portions of the gate electrodes, and the second dummy insulating layers disposed between the first dummy insulating layers, extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction, second separation regions dividing the stack structure and extending in the first direction, and cell contact plugs penetrating the horizontal portions and connected to the gate electrodes.

公开(公告)号：US11980028B2

公开(公告)日：2024-05-07

申请号：US17343330

申请日：2021-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim ,  Minjun Kang ,  Byunggon Park ,  Joongshik Shin

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B41/40 ,  G11C7/18 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.

公开(公告)号：US11616076B2

公开(公告)日：2023-03-28

申请号：US17216867

申请日：2021-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.