公开(公告)号：US20240014068A1

公开(公告)日：2024-01-11

申请号：US18217724

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee LEE ,  Byoungho KWON ,  Jonghyuk PARK ,  Boun YOON ,  Ilyoung YOON ,  Seokjun HONG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L21/76832 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76816 ,  H01L23/53295 ,  H10B12/315

Abstract: A semiconductor device includes a lower structure; an intermediate insulating structure on the lower structure; an intermediate interconnection structure penetrating through the intermediate insulating structure; an upper insulating structure on the intermediate insulating structure and the intermediate interconnection structure; and an upper conductive pattern penetrating through the upper insulating structure and electrically connected to the intermediate interconnection structure, wherein the intermediate insulating structure includes an intermediate etch-stop layer and an intermediate insulating layer thereon, the intermediate insulating layer includes first and second intermediate material layers, the second intermediate material layer having an upper surface coplanar with an upper surface of the first intermediate material layer, the intermediate interconnection structure penetrates through the first intermediate material layer and the intermediate etch-stop layer, and a material of the first intermediate material layer has a dielectric constant that is higher than a dielectric constant of a material of the second intermediate material layer.

公开(公告)号：US20220368560A1

公开(公告)日：2022-11-17

申请号：US17742456

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhee PARK ,  Wookwang LEE ,  Seungjoon KIM ,  Yanghee LEE ,  Youngmin PARK ,  Jaehyuk LEE

IPC: H04L12/40

Abstract: According to an embodiment, an electronic device comprises: a connecting terminal; a memory; and a processor connected to the connecting terminal and the memory, wherein the processor is configured to: identify a head unit of a vehicle connected to the connecting terminal; obtain information about a model of a vehicle or an installed operating system, associated with the identified head unit; and when the information about a specified tuning value for the identified head unit is stored in the memory, tune a register by using the specified tuning value.

公开(公告)号：US20210096659A1

公开(公告)日：2021-04-01

申请号：US17004147

申请日：2020-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongsoon PARK ,  Dongil SON ,  Jeonggyu JO ,  Yanghee LEE

IPC: G06F3/023 ,  G06F3/041 ,  G06F1/28

Abstract: Certain embodiments of the disclosure relate to an electronic device and a method for controlling a reset of a control IC. The electronic device may include a battery, at least one sensor, a control IC operatively connected to the at least one sensor, a reset IC operatively connected to the control IC, and a power supply unit operatively connected to the reset IC, wherein when an operation signal is not received from the control IC for a predetermined time, the reset IC is configured to control a voltage and/or current being applied to the control IC by controlling the power supply unit. Other certain embodiments are possible.

公开(公告)号：US20190244960A1

公开(公告)日：2019-08-08

申请号：US16386731

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L22/30 ,  H01L22/34 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

公开(公告)号：US20240194597A1

公开(公告)日：2024-06-13

申请号：US18527687

申请日：2023-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Yanghee LEE ,  Jonghyuk PARK

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L28/90 ,  H10B12/315

Abstract: A wiring structure includes a substrate; a lower insulating layer on the substrate; a lower wiring structure extending in a vertical direction and passing through the lower insulating layer; a spacer surrounding a side wall of the lower wiring structure; a capping insulating layer on the lower insulating layer; and a via structure extending in the vertical direction and passing through the capping insulating layer, wherein the via structure overlaps the lower wiring structure and the spacer in the vertical direction, and the via structure includes a protruding portion extending in the vertical direction and passing through at least a portion of the spacer.

公开(公告)号：US20190019742A1

公开(公告)日：2019-01-17

申请号：US15868544

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee LEE ,  Jonghyuk Park ,  Choongseob Shin ,  Hyojin Oh ,  Boun Yoon ,  IIyoung Yoon

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

公开(公告)号：US20230005935A1

公开(公告)日：2023-01-05

申请号：US17713327

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee LEE ,  Jonghyuk PARK ,  Ilyoung YOON ,  Boun YOON ,  Jeehwan HEO

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

公开(公告)号：US20200227419A1

公开(公告)日：2020-07-16

申请号：US16833914

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

IPC: H01L27/108 ,  H01L21/66

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

公开(公告)号：US20240147697A1

公开(公告)日：2024-05-02

申请号：US18308376

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee LEE ,  Byoungho KWON ,  Seongeun KIM ,  Sujeong KIM ,  Jonghyuk PARK ,  Ilyoung YOON ,  Woohyuk JANG ,  Byungsoo JOO

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/482

Abstract: A semiconductor device includes a substrate, a chip region in the substrate, a scribe lane region in the substrate, first active patterns in the chip region, a first device isolation pattern on the first active patterns, second active patterns in the scribe lane region, and a second device isolation pattern on the second active patterns. The scribe lane region is adjacent to the chip region. The first device isolation pattern includes a first device isolation material, and the second device isolation pattern includes a second device isolation material. The second device isolation material is different from the first device isolation material.

公开(公告)号：US20230389322A1

公开(公告)日：2023-11-30

申请号：US18133278

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Donghoon KWON ,  Hakseon KIM ,  Nakjin SON ,  Yanghee LEE ,  Juhyun LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.