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公开(公告)号：US11705203B2
公开(公告)日：2023-07-18
申请号：US17352095
申请日：2021-06-18
Applicant: SanDisk Technologies LLC
Inventor： Henry Chin , Hua-Ling Cynthia Hsu , Wei Zhao , Fanglin Zhang
IPC: G11C16/00 , G11C16/14 , G11C16/26 , G11C16/34 , G06F1/20 , G11C16/04 , H01L25/065 , H10B43/10 , H10B43/27
CPC classification number: G11C16/14 , G06F1/20 , G11C16/26 , G11C16/3459 , G11C16/0483 , H01L25/0657 , H01L2225/06562 , H10B43/10 , H10B43/27
Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.
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公开(公告)号：US20230083903A1
公开(公告)日：2023-03-16
申请号：US17557428
申请日：2021-12-21
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , A. Harihara Sravan , YenLung Li
Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.
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公开(公告)号：US20230081623A1
公开(公告)日：2023-03-16
申请号：US17666657
申请日：2022-02-08
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Hua-Ling Cynthia Hsu , Masaaki Higashitani , YenLung Li , Chen Chen
Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.
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4.发明申请公开(公告)号：US20230080999A1
公开(公告)日：2023-03-16
申请号：US17557433
申请日：2021-12-21
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , A. Harihara Sravan , YenLung Li
IPC: G06F12/0893 , G11C16/26
Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.
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公开(公告)号：US12197783B2
公开(公告)日：2025-01-14
申请号：US17732260
申请日：2022-04-28
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Fanglin Zhang
Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.
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Patent Agency Ranking
公开(公告)号：US20240282392A1
公开(公告)日：2024-08-22
申请号：US18346332
申请日：2023-07-03
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Frank Wanfang Tsai
CPC classification number: G11C16/3459 , G11C7/1039 , G11C16/102 , G11C16/26
Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. The shared transfer data latch can be used to transfer data for operations being performed on a first plane to use the data latches on the other plane for storing data for operations on the first plane.
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公开(公告)号：US11935599B2
公开(公告)日：2024-03-19
申请号：US17725911
申请日：2022-04-21
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Fanglin Zhang , Victor Avila
CPC classification number: G11C16/102 , G11C7/1051 , G11C16/08 , G11C16/24 , G11C16/26
Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.
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公开(公告)号：US11894068B2
公开(公告)日：2024-02-06
申请号：US17557236
申请日：2021-12-21
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu
CPC classification number: G11C16/26 , G06F11/1068 , G11C16/0483 , G11C16/24 , G11C11/5671 , H01L25/0657 , H01L2225/06562
Abstract: A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.
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公开(公告)号：US20220399072A1
公开(公告)日：2022-12-15
申请号：US17347953
申请日：2021-06-15
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Dana Lee
Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of data latches corresponding to a plurality of logical pages such that each encoded portion of data is distributed across two or more rows of data latches. The one or more control circuits are also configured to program the distributed encoded portions of data from the plurality of rows of data latches into non-volatile memory cells along a target word line.
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公开(公告)号：US10825526B1
公开(公告)日：2020-11-03
申请号：US16450042
申请日：2019-06-24
Applicant: SanDisk Technologies LLC
Inventor： YenLung Li , Hua-Ling Cynthia Hsu , Chen Chen , Min Peng
Abstract: In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.
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